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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C820A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0 to INT3, INTRTC, INTALM0 to INTALM4, INTKEY), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91C820A CMOS 16-Bit Microcontrollers TMP91C820AF/JT5AW4-S 1. Outline and Features TMP91C820A/JT5AW4 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91C820AF comes in a 144-pin flat package. JT5AW4-S comes in a 144-pad chip. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) Instruction mnemonics are upward compatible with TLCS-90 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4 channels (444 ns/2 bytes at 36 MHz) (2) Minimum instruction execution time: 111ns (at 36 MHz) (3) Built-in RAM: 8 Kbytes Built-in ROM: 8 Kbytes (However, 9999 (ROM code) has no internal ROM.) 91C820A-1 2006-01-31 TMP91C820A (4) External memory expansion * * * Expandable up to 136 Mbytes (Shared program/data area) Can simultaneously support 8- or 16-bit width external data bus ... Dynamic data bus sizing Separate bus system (5) 8-bit timers: 4 channels (6) 16-bit timer: 1 channel (7) General-purpose serial interface: 3 channels * * UART/synchronous mode IrDA (8) Serial bus interface: 1 channel I2C bus mode/clock synchronous select mode (9) LCD controller * * * Shift register/built-in RAM LCD driver Supported 16, 8 and 4 gray levels and black and white Hardware blinking cursor (10) SDRAM controller Supported 16-M, 64-M and 128-Mbit SDRAM with 16-bit data bus (11) Timer for real time clock (RTC) * Based on TC8521A (12) Key-on wakeup (Interrupt key input) (13) 10-bit AD converter: 8 channels (14) Watchdog timer (15) Melody/alarm generator * * * Melody: Output of clock 4 to 5461 Hz Alarm: Output of the 8 kinds of alarm pattern Output of the 5 kinds of interval interrupt (16) Chip select/wait controller: 4 channels (17) MMU * * * * Expandable up to 136 Mbytes (4 local area/8-bank method) 9 CPU interrupts: Software interrupt instruction and illegal instruction 31 internal interrupts: Seven selectable priority levels 6 external interrupts: Seven selectable priority levels (4-edge selectable) (18) Interrupts: 46 interrupts (19) Input/output ports: 77 pins (at external 16-bit data bus memory) (20) Standby function Three HALT modes: IDLE2 (Programmable), IDLE1, STOP (21) Hardware standby function (Power save function) 91C820A-2 2006-01-31 TMP91C820A (22) Triple-clock controller Clock doubler (DFM) Clock gear function: Select a high-frequency clock fc to fc/16 RTC (fs = 32.768 kHz) (23) Operating voltage * * * * VCC = 2.7 V to 3.6 V (fc = 27 MHz) VCC = 3.0 V to 3.6 V (fc max = 36 MHz) 144-pin QFP: P-LQFP144-1616-0.40C Chip form supply also available. For details, contact your local Toshiba sales representative. (24) Package 91C820A-3 2006-01-31 TMP91C820A ADTRG (P83) CPU (TLCS-900/L1) H-OSC Clock gear, clock doubler AN0 to AN7 (P80 to P87) AVCC, AVSS VREFH, VREFL TXD0 (PC0) RXD0 (PC1) SCLK0/ CTS0 (PC2) TXD1 (PC3) RXD1 (PC4) SCLK1/ CTS1 (PC5) OPTRX0, SCK (P70) OPTTX0, SO/SDA (P71) SI/SCL (P72) 10-bit 8ch AD converter DVCC [3] DVSS [7] X1 X2 EMU0 EMU1 XT1 XT2 RESET SIO/UART/IrDA (SIO0) SIO/UART (SIO1) Serial bus I/F (SBI) 8-bit timer (TMRA0) 8-bit timer (TMRA1) 8-bit timer (TMRA2) XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits F SR PC L-OSC AM0 AM1 Port 0 Port 1 Port 2 P00 to P07(D0 to D7) P10 to P17(D8 to D15) P20 to P27 (A16 to A23) P30 to P37(A8 to A15) P40 to P47(A0 to A7) RD (PZ0) WR (PZ1) HWR (PZ2) R / W , SRWR (PZ3) WAIT (P56) CS0 to CS3 , CS2A (P60 to P63) WDT (Watchdog timer) Port 3 Port 4 TXD2/TA0IN (PB0) RXD2/TA1OUT (PB1) 8-Kbyte SRAM Port 5/ Port Z CS/WAIT controller (4 blocks) TA3OUT/INT2 (PB5) 8-bit timer (TMRA3) Port 6 8-Kbyte MROM (Note) Port 7 MSK (P76), VEECLK (P77) CS2F (P73) CS2G (P74) CSEXA (P75) MMU Port 8 Port 9 Port A Port B Port C Port D Port E Port F D1BSCP (PD0) D2BLP (PD1) D3BFR (PD2) DLEBCD (PD3) DOFFB (PD4) LD0 to LD7 (PE0 to PE7) TB0OUT0/INT3 (PB6) LCD controller Interrupt controller EA24, CS2B (P64), EA25, CS2C (P65), CS2D / SRLB (P66), CS2E / SRUB (P67) CS2F (P73) CS2G (P74) CSEXA (P75) NMI / PS Keyboard I/F Melody/ alarm out RTC SIO/UART (SIO2) INT0 to INT3,TA3OUT, TB0OUT0 (PB3 to PB6) KI0 to KI7 (P90 to P97) KO0 to KO7 (PA0 to PA7) MLDALM (PD7) ALARM , MLDALM (PD6) TXD2/TA0IN (PB0) RXD2/TA1OUT (PB1) SDCKE (PF5) SDCLK (PF6) SDLDQM (PF3) SDUDQM (PF4) SDWE (PF2) SDRAS (PF0) SDCAS (PF1) SDCS (P61) 16-bit timer (TMRB0) SDRAM controller ( ): Initial function after reset Note: When ROM code is 9999, it has no ROM. Figure 1.1 TMP91C820A Block Diagram 91C820A-4 2006-01-31 TMP91C820A 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91C820A, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C820AF. P80/AN0 VREFH VREFL NMI /PS P91/KI1 P90/KI0 PF7 PF6/SDCLK DVSS7 PF5/SDCKE PF4/SDUDQM PF3/SDLDQM PD7/MLDALM PD6/ ALARM / MLDALM P77/VEECLK P76/MSK P75/ CSEXA P74/ CS2G P73/ CS2F DVCC3 P72/SI/SCL P71/SO/SDA/OPTTX0 P70/SCK/OPTRX0 P67/ CS2E / SRUB P66/ CS2D / SRLB P65/EA25/ CS2C P64/EA24/ CS2B P63/ CS3 DVSS6 P62/ CS2 / CS2A P61/ CS1/ SDCS P60/ CS0 P56/ WAIT PZ3/ R/W / SRWE PZ2/ HWR PZ1/ WR 125 135 130 120 115 40 60 65 45 50 SDWE /PF2 D1BSCP/PD0 AM0 DVCC1 X2 DVSS2 X1 AM1 Figure 2.1.1 Pin Assignment Diagram (144-pin QFP) XT1 XT2 EMU0 EMU1 D2BLP/PD1 D3BFR/PD2 DLEBCD/PD3 DOFFB/PD4 LD0/PE0 LD1/PE1 LD2/PE2 LD3/PE3 LD4/PE4 LD5/PE5 LD6/PE6 LD7/PE7 DVSS3 P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 SDRAS /PF0 SDCAS /PF1 RESET 55 70 P81/AN1 P82/AN2 P83/AN3/ ADTRG P84/AN4 P85/AN5 P86/AN6 P87/AN7 AVSS AVCC KI2/P92 KI3/P93 KI4/P94 KI5/P95 KI6/P96 KI7/P97 KO0/PA0 KO1/PA1 KO2/PA2 KO3/PA3 KO4/PA4 KO5/PA5 KO6/PA6 KO7/PA7 TXD2/TA0IN/PB0 RXD2/TA1OUT/PB1 INT0/PB3 INT1/PB4 DVSS1 TA3OUT/INT2/PB5 TB0OUT0/INT3/PB6 TXD0/PC0 RXD0/PC1 SCLK0/ CTS0 /PC2 TXD1/PC3 RXD1/PC4 SCLK1/ CTS1 /PC5 1 140 110 105 5 100 10 95 15 TMP91C820AF QFP144 90 20 Top view 85 25 80 30 75 35 PZ0/ RD P27/A23 P26/A22 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 DVSS5 P20/A16 DVCC2 P37/A15 P36/A14 P35/A13 P34/A12 P33/A11 P32/A10 P31/A9 P30/A8 P47/A7 P46/A6 P45/A5 P44/A4 P43/A3 P42/A2 P41/A1 P40/A0 D15/P17 DVSS4 D14/P16 D13/P15 D12/P14 D11/P13 D10/P12 D9/P11 D8/P10 91C820A-5 2006-01-31 TMP91C820A 2.2 PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PAD layout Unit: m (Chip size 5.75 mm x 5.63 mm) Name P81 P82 P83 P84 P85 P86 P87 AVSS AVCC P92 P93 P94 P95 P96 P97 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB3 PB4 DVSS1 PB5 PB6 PC0 PC1 PC2 PC3 PC4 PC5 PF0 PF1 PF2 PD0 AM0 DVCC1 X2 DVSS2 X1 AM1 RESET X Point Y Point -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2742 -2194 -2068 -1954 -1840 -1726 -1612 -1410 -1244 -1079 -963 -849 -734 2128 2004 1888 1774 1660 1546 1432 1318 1204 892 778 664 550 436 322 208 94 -20 -134 -248 -362 -476 -590 -704 -818 -932 -1046 -1210 -1324 -1438 -1552 -1666 -1780 -1894 -2010 -2134 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 PIN No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name XT2 EMU0 EMU1 PD1 PD2 PD3 PD4 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 DVSS3 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 DVSS4 P17 P40 P41 P42 P43 P44 P45 P46 P47 P30 P31 P32 P33 P34 P35 P36 X Point Y Point -485 -370 -256 -142 -28 86 200 314 428 542 656 770 884 998 1112 1246 1378 1492 1606 1720 1834 1948 2062 2188 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2682 -2134 -2010 -1894 -1780 -1666 -1552 -1438 -1318 -1066 -952 -838 -724 -610 -496 -382 -268 -154 -40 74 188 302 416 530 644 PIN No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name P37 DVCC2 P20 DVSS5 P21 P22 P23 P24 P25 P26 P27 PZ0 PZ1 PZ2 PZ3 P56 P60 P61 P62 DVSS6 P63 P64 P65 P66 P67 P70 P71 P72 DVCC3 P73 P74 P75 P76 P77 PD6 PD7 PF3 PF4 PF5 DVSS7 PF6 PF7 P90 P91 NMI X Point 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2736 2188 2062 1948 1834 1720 1606 1492 1378 1264 1150 1036 922 808 694 580 382 268 68 -46 -160 -274 -388 -520 -634 -748 -862 -976 -1090 -1204 -1318 -1432 -1546 -1660 -1954 -2068 -2194 Y Point 758 872 986 1202 1318 1432 1546 1660 1774 1888 2004 2128 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 2676 VREFL VREFH P80 XT1 91C820A-6 2006-01-31 TMP91C820A 2.3 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.3.1 Pin Names and Functions (1/4) Pin Name P00 to P07 D0 to D7 P10 to P17 D8 to D15 P20 to P27 A16 to A23 P30 to P37 A8 to A15 P40 o P47 A0 to A7 PZ0 RD Number of Pins 8 8 I/O I/O I/O I/O I/O Functions Port 0: I/O port that allows I/O to be selected at the bit level Data (Lower): Bits 0 to 7 of data bus Port 1: I/O port that allows I/O to be selected at the bit level (When used to the external 8-bit bus) Data (Upper): Bits 8 to15 of data bus Port 2: I/O port Address: Bits 16 to 23 of address bus Port 3: I/O port Address: Bits 8 to 15 of address bus Port 4: I/O port Address: Bits 0 to 7 of address bus Port Z0: Output port Read: Strobe signal for reading external memory Port Z1: Output port Write: Strobe signal for writing data to pins D0 to D7 Port Z2: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins D8 to D15 Port Z3: I/O port (with pull-up resistor) Read/write: 1 represents read or dummy cycle; 0 represents write cycle. Write for SRAM: Strobe signal for writing data. Port 56: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port 60: Output port Chip select 0: Outputs 0 when address is within specified address area. Port 61: Output port Chip select 1: Outputs 0 when address is within specified address area Chip select for SDRAM: Outputs 0 when address is within SDRAM address area Port 62: Output port Chip select 2: Outputs 0 when address is within specified address area Expand chip select 2A: Outputs 0 when address is within specified address area Port 63: Output port Chip select 3: Outputs 0 when address is within specified address area Port 64: Output port Chip select 24: Outputs 0 when address is within specified address area Expand chip select 2B: Outputs 0 when address is within specified address area Port 65: Output port Chip select 25: Outputs 0 when address is within specified address area Expand chip select 2C: Outputs 0 when address is within specified address area Port 66: Output port Expand chip select 2D: Outputs 0 when address is within specified address area Lower byte enable for SRAM: Outputs 0 when lower data is enable. Port 67: Output port Expand chip select 2E: Outputs 0 when address is within specified address area Upper byte enable for SRAM: Outputs 0 when upper data is enable. 8 8 8 1 1 1 1 Output Output Output Output Output Output Output Output Output Output I/O Output I/O Output Output PZ1 WR PZ2 HWR PZ3 R/ W SRWR P56 WAIT 1 1 1 I/O Input Output Output Output Output Output P60 CS0 P61 CS1 SDCS P62 CS2 CS2A 1 Output Output Output P63 CS3 1 1 Output Output Output Output Output P64 EA24 CS2B P65 EA25 CS2C 1 Output Output Output P66 CS2D SRLB 1 Output Output Output P67 CS2E SRUB 1 Output Output Output 91C820A-7 2006-01-31 TMP91C820A Table 2.3.2 Pin Names and Functions (2/4) Pin Name P70 SCK OPTRX0 P71 S0 SDA OPTRX0 P72 SI SCL P73 CS2F Number of Pins 1 I/O I/O I/O Input Port 70: I/O port Functions Serial bus interface clock I/O data at SIO mode Serial 0 recive data Port 71: I/O port Serial bus interface send data at SIO mode Serial bus interface send/recive data at I C bus mode (Open-drain output mode by programmable) Serial 0 send data Port 72: I/O port Serial bus interface recive data at SIO mode Serial bus interface clock I/O data at I C bus mode (Open-drain output mode by programmable) Port 73: I/O port Expand chip select 2F: Outputs 0 when address is within specified address area Port 74: I/O port Expand chip select 2G: Outputs 0 when address is within specified address area Port 75: I/O port Expand chip select EXA: Outputs 0 when address is within specified address area Port 76: I/O port Mask: Use for disable to output VEECLK for LCD driver Port 77: I/O port Output 32.768 kHz clock to LCD driver. (Can be disabled by MSK pin.) Port 80 to 87: Pin used to input ports Analog input 0 to 7: Pin used to input to AD conveter AD trigger: Signal used to request AD start (with used to P83) Port 90 to 97: Pin used to input ports Key input 0 to 7: Pin used of key-on wakeup 0 to 7 (Schmitt input, with pull-up resistor) Port A0 to A7: Pin used to output ports Key output 0 to 7: Pin used of key-scan strobe 0 to 7 Port B0: I/O port 8-bit timer 0 input: Timer 0 input Serial 2 send data: Open-drain output pin by programmable Port B1: I/O port 8-bit timer 1 output: Timer 1 output Serial 2 receive data Port B3: I/O port Interrupt request pin0: Interrupt request pin with programmable level/rising/falling edge Port B4: I/O port Interrupt request pin1: Interrupt request pin with programmable rising/falling edge 2 2 1 I/O Output I/O Output 1 I/O Input I/O 1 1 1 I/O Output I/O Output I/O Output P74 CS2G P75 CSEXA P76 MSK P77 VEECLK P80 to P87 AN0 to AN7 ADTRG 1 1 8 I/O Input I/O Output Input Input Input P90 to P97 KI0 to KI7 PA0 to PA7 KO0 to KO7 PB0 TA0IN TXD2 PB1 TA1OUT RXD2 PB3 INT0 PB4 INT1 8 Input Input 8 1 Output Output I/O Input Output 1 I/O Output Input 1 I/O Input 1 I/O Input 91C820A-8 2006-01-31 TMP91C820A Table 2.3.3 Pin Names and Functions (3/4) Pin Name PB5 INT2 TA3OUT PB6 INT3 TB0OUT0 PC0 TXD0 PC1 RXD0 PC2 SCLK0 CTS0 Number of Pins 1 I/O I/O Input Output Port B5: I/O port Functions Interrupt request pin2: Interrupt request pin with programmable rising/falling edge 8-bit timer 3 output: Timer 3 output Port B6: I/O port Interrupt request pin3: Interrupt request pin with programmable rising/falling edge Timer B0 output Port C0: I/O port Serial 0 send data: Open-drain output pin by programmable Port C1: I/O port Serial 0 receive data Port C2: I/O port Serial 0 clock I/O Serial 0 data send enable (Clear to send) Port C3: I/O port Serial 1 send data (Open-drain output pin by programmable) Port C4: I/O port Serial 1 receive data Port C5: I/O port Serial 1 clock I/O Serial 1 data send enable (Clear to send) Port D0: Output port LCD driver output pin Port D1: Output port LCD driver output pin Port D2: Output port LCD driver output pin Port D3: Output port LCD driver output pin Port D4: Output port LCD driver output pin Port D6: Output port RTC alarm output pin Melody/alarm output pin (Inverted) Port D7: Output port Melody/alarm output pin Port E0 to E7: I/O port Data bus for LCD driver Port F0: Output port Row address storobe for SDRAM: Outputs 0 when address is within SDRAM address area Port F1: Output port Column address storobe for SDRAM: Outputs 0 when address is within SDRAM address area 1 I/O Input Outout 1 1 1 I/O Output I/O Input I/O I/O Input PC3 TXD1 PC4 RXD1 PC5 SCLK1 CTS1 1 1 1 I/O Output I/O Input I/O I/O Input PD0 D1BSCP PD1 D2BLP PD2 D3BFR PD3 DLEBCD PD4 DOFFB PD6 ALARM MLDALM 1 1 1 1 1 1 Output Output Output Output Output Output Output Output Output Output Output Output Output PD7 MLDALM PE0 to PE7 LD0 to LD7 PF0 SDRAS 1 8 1 Output Output I/O Output I/O Output PF1 SDCAS 1 I/O Output 91C820A-9 2006-01-31 TMP91C820A Table 2.3.4 Pin Names and Functions (4/4) Pin Name PF2 SDWE Number of Pins 1 1 1 1 1 1 1 I/O Output Output Output Output Output Output Output Output Output Output Output Input Input Port F2: Output port Write enable for SDRAM Port F3: Output port Lower data enable for SDRAM Port F4: Output port Upper data enable for SDRAM Port F5: Output port Clock enable for SDRAM Port F6: Output port Clock for SDRAM Port F7: Output port Functions PF3 SDLDQM PF4 SDUDQM PF5 SDCKE PF6 SDCLK PF7 PS NMI Power save mode setting terminal Non-maskable interrupt request: Interrupt request pin with programmable falling edge level or with both edge levels programmable Operation mode: Fixed to AM1 = 1, AM0 = 1 when using internal ROM (when ROM code is 9999, setting is prohibitted). Fixed to AM1 = 0, AM0 = 1 when using external ROM by 16-bit external bus, or 8or 16-bit dynamic sizing. Fixed to AM1 = 0, AM0 = 0 when using external ROM by 8-bit external bus. (Note) AM0 to AM1 2 Input EMU0 EMU1 RESET 1 1 1 1 1 2 2 1 1 3 7 Output Output Input Input Input I/O I/O Open pin Open pin Reset: Initializes TMP91C820A (with pull-up resistor). Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) High-frequency oscillator connection pins Low-frequency oscillator connection pins Power supply pin for AD converter GND pin for AD converter (0 V) Power supply pins (All VCC pins should be connecyed with the power supply pin). GND pins (All pins should be connected with GND (0 V).) VREFH VREFL X1/X2 XT1/XT2 AVCC AVSS DVCC DVSS Note: Please input 1 into NMI / PS pin, because NMI / PS = 0 means power save mode after reset. 91C820A-10 2006-01-31 TMP91C820A 3. Operation This following describes block by block the functions and operation of the TMP91C820A. Notes and restrictions for eatch book are outlined in 6 "Points of Note and Restrictions" at the end of this manual. 3.1 CPU The TMP91C820A incorporates a high-performance 16-bit CPU (The 900/L1 CPU). For CPU operation, see the "TLCS-900/L1 CPU". The following describe the unique function of the CPU used in the TMP91C820A; these functions are not covered in the TLCS-900/L1 CPU section. 3.1.1 Reset When resetting the TMP91C820A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level for at least 10 system clocks (9s at 36MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 x 1/2). When the reset is accept, the CPU: * Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> PC<15:8> * * * * Value at FFFF00H address Value at FFFF01H address PC<23:16> Value at FFFF02H address Sets the stack pointer (XSP) to 100H. Sets bits When reset is released,the CPU starts executing instructions in accordance with the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows. Initializes the internal I/O registers. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Note: The CPU internal register (except to PC, SR, XSP) and internal RAM data do not change by resetting. Figure 3.1.1 is a reset timing of the TMP91C820A-9999. 91C820A-11 2006-01-31 fFPH Sampling Sampling RESET A23 to A0 0FFFF00H CS0, CS1, CS3 CS2 D0 to D15 Data-in Data-in Read RD (After reset released, startting 2 waits read cycle) Figure 3.1.1 TMP91C820A-9999 Reset Timing Example (The case of using external ROM) Data-out 91C820A-12 (PZ2 input mode) D0 to D15 WR Write HWR XT1, XT2 : Pull up (Internal) : High-Z TMP91C820A 2006-01-31 TMP91C820A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91C820A. 000000H Internal I/O (4 Kbytes) 000100H 000FE0H 001000H Internal RAM (8 Kbytes) 003000H Direct area(n) 64-Kbyte area (nn) 010000H External memory FFE000H Mask ROM (8 Kbytes) FFFF00H FFFFFFH Vector table (256 bytes) 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) ( = Internal area) Figure 3.2.1 Memory Map Note: Address 000FE0H to 000FFFH is assigned for the external memory area of built-in RAM type LCD driver. And when ROM code is 9999, internal mask ROM area also defines external memory area. 91C820A-13 2006-01-31 TMP91C820A 3.3 Triple Clock Function and Standby Function TMP91C820A contains (1) Clock gear, (2) Clock doubler (DFM), (3) Standby controller, and (4) Noise-reducing circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 SFRs System Clock Controller Prescaler Clock Controller Clock Doubler (DFM) Noise Reduction Circuits Standby Controller 91C820A-14 2006-01-31 TMP91C820A The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (The X1, X2, XT1 and XT2 pins and DFM). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Instruction SLOW mode (fs/2) Dual clock mode transition fiigure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fOSCH/gear value/2) Instruction *Note Interrupt Instruction Interrupt SLOW mode (fs/2) STOP mode (Stops all circuits) Instruction Instruction *Note IDLE2 mode (I/O operate) Instruction Interrupt Instruction Instruction Interrupt Instruction IDLE1 mode Instruction (Operate oscillator and DFM) Interrupt NORMAL mode (4 x fOSCH/gear value/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Using DFM (c) Triple clock mode transition figure Interrupt Note 1: It's prohibited to control DFM in SLOW mode when shifting from SLOW mode to NORMAL mode with use of DFM. (DFM start up/stop/change write to DFMCR0 Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 91C820A-15 2006-01-31 TMP91C820A 3.3.1 Block Diagram of System Clock SYSCR0 fc/16 SYSCR0 /2 fSYS SYSCR0 SYSCR1 /2 /4 /8 /16 Clock gear SYSCR1 DFMCR0 Prescaler CPU RAM Interrupt controller SIO0 to 2 ADC Prescaler WDT SBI T Prescaler I/O ports SDRAMC ROM RTC fs LCDC MLD/ALM Figure 3.3.2 Block Diagram of System Clock 91C820A-16 2006-01-31 TMP91C820A 3.3.2 SFRs 7 SYSCR0 Bit symbol (00E0H) Read/Write After reset Function XEN 1 6 XTEN 1 5 RXEN 1 4 RXTEN 0 Lowfrequency oscillator (fs) after release of STOP mode 3 RSYSCK R/W 0 2 WUEF 0 1 PRCK1 0 00: fFPH (Note 2) 01: Reserved 10: fc/16 11: Reserved 0 PRCK0 0 HighLowHighfrequency frequency frequency oscillator (fc) oscillator (fs) oscillator (fc) after release 0: Stop 0: Stop 1: Oscillation 1: Oscillation of STOP mode (Note 1) Selects clock Warm-up after release timer of STOP 0: Write mode don't 0: fc care 1: fs 1: Write 0: Stop 0: Stop start 1: Oscillation 1: Oscillation timer 0: Read end warm up 1: Read do not end warm up Select prescaler clock 7 SYSCR1 Bit symbol (00E1H) Read/Write After reset Function 6 5 4 3 SYSCK 0 Select system clock 0: fc 1: fs 2 GEAR2 R/W 1 1 GEAR1 0 0 GEAR0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 Bit symbol (00E2H) Read/Write After reset Function PSENV R/W 0 1:Disable 0:Power save mode enable (Note 3) 6 5 WUPTM1 R/W 1 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 SELDRV R/W 0 1: STOP 0: IDLE1 (Note 4) 0 DRVE R/W 0 Pin state control in STOP/IDLE1 mode 0: I/O off 1: Remains the state before halt Warm-up timer 00: Reserved 01: 28 inputted frequency 10:214 11:216 Note 1: Note 2: Note 3: Note 4: By reset, low-frequency oscillator is enabled. It's prohibit to use to fc/16 prescaler clock when SBI block use. (I C bus and clock synchronous.) When use NMI / PS pin as NMI function, set 2 Figure 3.3.3 SFR for System Clock 91C820A-17 2006-01-31 TMP91C820A Symbol Name Address 7 ACT1 R/W 0 6 ACT0 R/W 0 LUP 5 DLUPFG R 0 4 DLUPTM R/W 0 Lockup time 0: 212/fOSCH 3 2 1 0 DFM DFMCR0 control register 0 E8H DFM select Lockup fFPH status flag 00 STOP STOP fOSCH 01 RUN RUN f OSCH 0: End 10 1: Not end 1: 2 /fOSCH 10 RUN STOP 11 RUN STOP D7 DFM DFMCR1 control register 1 E9H R/W 0 fDFM fOSCH D6 R/W 0 D5 R/W 0 D4 R/W 1 D3 R/W 0 D2 R/W 0 D1 R/W 1 D0 R/W 1 DFM revision Input frequency 4 to 9 MHz (at 2.7 V to 3.6 V): Write 0BH Figure 3.3.4 SFR for DFM Limitation point on the use of DFM 1. It's prohibited to execute DFM enable/disable control in the SLOW mode (fs) (Write to DFMCR0 LD LD (DFMCR0), C0H (DFMCR0), 00H ; ; Change the clock fDFM to fOSCH. DFM stop. 2. 3. If you stop high-frequency oscillator during using DFM (DFMCR0 Please refer to 3.3.5 "Clock Doubler (DFM)" for the details. 91C820A-18 2006-01-31 TMP91C820A 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function R 0 Protect flag 0: OFF 1: ON 6 R/W 0 LCDC 5 AHOLD R/W 0 4 TA3MLDE R/W 0 3 - R/W 0 2 EXTIN R/W 0 1 DRVOSCH 0 DRVOSCL PROTECT TA3LCDE R/W 1 fc oscillator driver ability 1: Normal 0: Weak R/W 1 fs oscillator driver ability 1: Normal 0: Weak Address Source clock hold (Note) 0: 32 kHz 0: Disable 1: TA3OUT 1: Enable Melody/alarm Always write 1: External source clock "0". clock 0: 32 kHz 1: TA3OUT Bit symbol EMCCR1 (00E4H) Read/Write After reset Function EMCCR2 (00E5H) Bit symbol Read/Write After reset Function EMCCR3 (00E6H) Bit symbol Read/Write After reset Function ENFROM R/W 0 CS1A area detect control 0: Disable 1: Enable Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write ENDROM R/W 0 CS2B 2G area detect control 0: Disable 1: Enable ENPROM R/W 0 CS2A area detect control 0: Disable 1: Enable FFLAG R/W 0 CS1A write operation flag DFLAG PFLAG R/W 0 CS2B 2G write operation flag R/W 0 CS2A write operation flag When reading 0: Not written 1: Written When writing 0: Clear flag Note1: When getting access to the logic address 000000H to 000FDFH, 001000H to 002FFFH and FFE000H to FFFFFFH, A0 to A23 holds the previous address of external access. Note2: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0 Figure 3.3.5 SFR for Noise Reducing 91C820A-19 2006-01-31 TMP91C820A 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 Note 1: When using an oscillator (Other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.1 Warm-up Times Warm-up Time SYSCR2 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to NORMAL Mode 7.1 [s] Change to SLOW Mode 7.8 500 2000 [ms] [ms] [ms] at fOSCH = 36 MHz, fs = 32.768 kHz 0.455 [ms] 1.820 [ms] 91C820A-20 2006-01-31 TMP91C820A Example 1: SYSCR0 SYSCR1 SYSCR2 Setting the clock Changing from high frequency (fc) to low frequency (fs). EQU EQU EQU LD SET SET 00E0H 00E1H 00E2H (SYSCR2), -X11- - - -B 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) ; ; ; ; ; ; ; Sets warm-up time to 2 /fs. Enables low-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fc to fs. Disables high-frequency oscillation. 16 WUP: BIT JR SET RES X: Don't care, -: No change Warm-up timer End of warm-up timer Counts up by fSYS Counts up by fs fc fs Enables low frequency Clears and starts warm-up timer Chages fSYS from fc to fs End of warm-up timer Disables high frequency 91C820A-21 2006-01-31 TMP91C820A Example 2: SYSCR0 SYSCR1 SYSCR2 Setting the clock Changing from low frequency (fs) to high frequency (fc). EQU EQU EQU LD SET SET 00E0H 00E1H 00E2H (SYSCR2), -X10- - - -B 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) ; ; ; ; ; ; ; Sets warm-up time to 2 /fc. Enables high-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fs to fc. Disables low-frequency oscillation. 14 WUP: BIT JR RES RES X: Don't care, -: No change Warm-up timer End of warm-up timer Counts up by fSYS Counts up by fOSCH fs fc Enables high frequency Clears and starts warm-up timer Chages fSYS from fs to fc End of warm-up timer Disables low frequency 91C820A-22 2006-01-31 TMP91C820A (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 Example 3: SYSCR1 Changing to a high-frequency gear EQU LD LD X: Don't care 00E1H (SYSCR1), XXXX0000B (SYSCR1), XXXX0100B ; ; Changes fSYS to fc/2. Changes fSYS to fc/32. (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 (Example) SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction. Instruction to be executed after clock gear has changed. 91C820A-23 2006-01-31 TMP91C820A 3.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1,SBI) there is a prescaler which can divide the clock. The T clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 2. The setting of the SYSCR0 3.3.5 Clock Doubler (DFM) DFM outputs the fDFM clock signal, which is four times as fast as fOSCH. It can use the low-frequency oscillator, even though the internal clock is high frequency. A reset initializes DFM to stop status, setting to DFMCR0 register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lockup time. The following example shows how DFM is used. DFMCR0 DFMCR1 EQU EQU LD LD LUP: BIT JR LD X: Don't care 00E8H 00E9H (DFMCR1), 0BH (DFMCR0), 01X0XXXXB 5, (DFMCR0) NZ, LUP (DFMCR0), 10X0XXXXB ; ; ; ; ; Parameter setting. Set lockup time to 2 /4 MHz. Enables DFM operation and starts lockup. Detects end of lockup. Changes fc from 4 MHz to 16 MHz. 12 ACT1 to ACT0 DFM output: fDFM Lockup timer 01 10 Counts up by fOSCH During lockup After lockup Starts DFM operation. Starts lockup. Changes from 4 MHz to 16 MHz. Ends of lockup Note: Input frequency limitation and correction for DFM. Recommend to use input frequency (High-speed oscillation) for DFM in the following condition. fOSCH = 4 MHz to 9 MHz (Vcc = 2.7 V to 3.6 V): Write 0BH to DFMCR1. 91C820A-24 2006-01-31 TMP91C820A Limitation point on the use of DFM 1. It's prohibited to execute DFM enable/disable control in the SLOW mode (fs) (Write to DFMCR0 LD LD (DFMCR0), C0H (DFMCR0), 00H ; ; Change the clock fDFM to fOSCH. DFM stop. 2. 3. If you stop high-frequency oscillator during using DFM (DFMCR0 DFM start up DFM use mode (fDFM) WUP: LD BIT JR LD LD BIT JR LD (SYSCR0), 11- - -1- -B 2, (SYSCR0) NZ, WUP (SYSCR1), - - - -0- - -B (DFMCR0), 01-0- - - -B 5, (DFMCR0) NZ, LUP (DFMCR0), 10-0- - - -B ; ; ; ; ; ; ; ; High-frequency oscillator start-up/warm-up start. Check for the flag of lockup end. Change the system clock fS to fOSCH. DFM start-up/lockup start. Check for the flag of lockup end. Change the system clock. LUP: (OK) Low-frequency oscillator operation mode (fs) (high-frequency oscillator operate) High-frequency oscillator operation mode (fOSCH) DFM start up DFM use mode (fDFM) LD LD BIT JR LD (SYSCR1), - - - -0- - -B (DFMCR0), 01-0- - - -B 5, (DFMCR0) NZ, LUP (DFMCR0), 10-0- - - -B ; ; ; ; ; Change the system clock fs to fOSCH. DFM start-up/lockup start. Check for the flag of lockup end. Change the system clock fOSCH to fDFM. LUP: (Error) Low-frequency oscillator operation mode (fs) (High-frequency oscillator stop) High-frequency oscillator start up DFM start up DFM use mode (fDFM) WUP: LD BIT JR LD BIT JR LD LD (SYSCR0), 11- - -1- -B 2, (SYSCR0) NZ, WUP (DFMCR0), 01-0- - - -B 5, (DFMCR0) NZ, LUP (DFMCR0), 10-0- - - -B (SYSCR1), - - - -0- - -B ; ; ; ; ; ; ; ; High-frequency oscillator start-up/warm-up start. Check for the flag of lockup end. DFM start-up/lockup start. Check for the flag of lockup end. Change the internal clock fOSCH to fDFM. Change the system clock fS to fDFM. LUP: 91C820A-25 2006-01-31 TMP91C820A (2) Change/stop control (OK) DFM use mode (fDFM) High-frequency oscillator operation mode (fOSCH) DFM stop Low-frequency oscillator operation mode (fs) High-frequency oscillator stop LD LD LD LD (DFMCR0), 11- - - - - -B (DFMCR0), 00- - - - - -B (SYSCR1), - - - -1- - -B (SYSCR0), 0- - - - - - -B ; ; ; ; Change the system clock fDFM to fOSCH. DFM stop. Change the system clock fOSCH to fs. High-frequency oscillator stop. (Error) DFM use mode (fDFM) Low-frequency oscillator operation mode (fs) DFM stop High-frequency oscillator stop LD LD LD LD (SYSCR1), - - - -1- - -B (DFMCR0), 11- - - - - -B (DFMCR0), 00- - - - - -B (SYSCR0), 0- - - - - - -B ; ; ; ; Change the system clock fDFM to fs. Change the internal clock (fc) fDFM to fOSCH. DFM stop. High-frequency oscillator stop. (OK) DFM use mode (fDFM) Set the STOP mode High-frequency oscillator operation mode (fOSCH) DFM stop Halt (High-frequency oscillator stop) LD LD LD HALT (SYSCR2), - - - -01- -B (DFMCR0), 11- - - - - -B (DFMCR0), 00- - - - - -B ; ; ; ; Set the STOP mode. (This command can execute before use of DFM.) Change the system clock fDFM to fOSCH. DFM stop. Shift to STOP mode. (Error) DFM use mode (fDFM) Set the STOP mode Halt (High-frequency oscillator stop) LD HALT (SYSCR2), - - - -01- -B ; ; Set the STOP mode. (This command can execute before use of DFM.) Shift to STOP mode. 91C820A-26 2006-01-31 TMP91C820A 3.3.6 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) Runaway provision with SFR protection register (5) Runaway provision with ROM protection register The above functions are performed by making the appropriate settings in the EMCCR0 to EMCCR3 registers. (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 Resonator C2 X2 pin X1 pin Enable oscillation (STOP + EMCCR0 (Setting method) The drivability of the oscillator is reduced by writing 0 to EMCCR0 91C820A-27 2006-01-31 TMP91C820A (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin Enable oscillation EMCCR0 C1 Resonator (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0 (3) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation (STOP + EMCCR0 EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing 1 to EMCCR0 Note: Do not write EMCCR0 91C820A-28 2006-01-31 TMP91C820A (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller, MMU) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. 3. 4. MMU LOCAL0/1/2/3 Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0, EMCCR3 DFM DFMCR0/1 (Operation explanation) Execute and release of protection (Write operation to specified SFR) become possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st-KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd-KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0 91C820A-29 2006-01-31 TMP91C820A (5) Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When writes operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. Three kinds of ROM is fixed as for flash ROM (Option program ROM), data ROM, program ROM are as follows on the logical address memory map. 1. Flash ROM: Address 400000H to 7FFFFFH 2. Data ROM: Address 800000H to BFFFFFH 3. Program ROM: Address C00000H to FFFFFFH For these address, admission/prohibition of detection of write operation sets it up with EMCCR3 91C820A-30 2006-01-31 TMP91C820A 3.3.7 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 Table 3.3.2 SFR Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRB0 SIO0 SIO1 AD converter WDT SBI SFR TA01RUN b. IDLE1: Only the oscillator and the RTC (Real time clock) and MLD continue to operate. c. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.3.3. Table 3.3.3 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA,TMRB0 SIO, SBI Block AD converter WDT LCDC, SDRAMC Interrupt controller RTC, MLD Available to select operation block IDLE2 11 Stop Keep the state when the HALT instruction was executed. IDLE1 10 STOP 01 Table 3.3.6 and Table 3.3.7 Stop Operate Operational available 91C820A-31 2006-01-31 TMP91C820A (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register Note: Usually, interrupts can release all halt status. However, the interrupts ( NMI , INT0 to INT3, INTKEY, INTRTC, INTALM0 to INTALM4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to the HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. * Releasing by resetting Releasing all halt status is executed by resetting. When the stop mode is released by reset, it is necessry enough resetting time (See Table 3.3.5) to set the operation of the oscillator to be stable. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the HALT instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the HALT instruction is executed.) 91C820A-32 2006-01-31 TMP91C820A Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT mode NMI INTWDT Source of halt state clearance Interrupt Enabled (Interrupt level) (Interrupt mask) Interrupt Disabled (Interrupt level) < (Interrupt mask) IDLE2 IDLE1 x x x x x x x STOP *1 IDLE2 - - IDLE1 - - STOP - - x * x x x x x * x x x 1 1 INT0 to INT3 (Note 1) INTALM0 to INTALM4 Interrupt x x x x x x x x *1 x x x x x INTTA0 to INTTA3, INTTB00 to INTTB01 INTRX0 to INTRX2, TX0 to TX2 INTSS0 to INTSS2 INTAD INTKEY INTRTC INTSBI INTLCD RESET x x x x *1 x x x Initialize LSI. : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. x: It can not be used to release the HALT mode . -: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. (Example releasing IDLE1 mode) An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (PBFC), 08H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 88H ; Sets PB3 to INT0. ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91C820A-33 2006-01-31 TMP91C820A (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC, MLD continue to operate. The system clock in the MCU stops. The pin status in the IDLE1 mode is depended on setting the register SYSCR2 X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release IDLE1 mode Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91C820A-34 2006-01-31 TMP91C820A c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 Warm-up time X1 A0 to A23 D0 to D15 RD Data Data WR Interrupt for release STOP mode Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode at fOSCH = 36 MHz, fs = 32.768 kHz SYSCR0 0 (fc) 1 (fs) SYSCR2 7.1 s 7.8 ms 8 10 (214) 0.455 ms 500 ms 11 (216) 1.820 ms 2000 ms 91C820A-35 2006-01-31 TMP91C820A (Setting example) The STOP mode is entered when the low frequency operates, and high frequency operates after releasing due to NMI. Address SYSCR0 SYSCR1 SYSCR2 8FFDH 9000H 9002H 9005H NMI EQU EQU EQU LD LD LD HALT 00E0H 00E1H 00E2H (SYSCR1), 08H (SYSCR2), -X1001X1B (SYSCR0), 011000 - -B ; fSYS = fs/2. 14 ; Sets warm-up time to 2 /fOSCH. ; Operates high-frequency after released. Clears and starts hit warm-up timer (High frequency) End NMI interrupt routine 9006H LD XX, XX RETI -: No change Note: When different modes are used before and after STOP mode as the above mentioned, there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of halt instruction (during 6 state). In the system which accepts the interrupts during execution HALT instruction, set the same operation mode before and after the STOP mode. 91C820A-36 2006-01-31 TMP91C820A Table 3.3.6 Input buffer state table (1/2) When the CPU is operating When When Used as Used as function Input Port Pin ON upon port read ON upon external read Input Buffer State In HALT mode In HALT mode(IDLE1/STOP) (IDLE2) Condition A (Note) Condition B (Note) When When When When When When Used Used as Used as Used as Used as Used as as Input function function function Input Port Input Port Port Pin Pin Pin Port Name Input Function Name During Reset P00-P07 D0-D7 OFF 8bit start: OFF 16bit start: ON Built-in ROM start: ON 8bit start: OFF 16bit start: OFF Built-in ROM start: ON P10-P17 D8-D15 ON upon external read of LCDC OFF OFF P20-P27 P30-P37 - - OFF OFF P40-P47 - - - - - ON PZ2 (*1) PZ3 (*1) P56 (*1) P70 P71 P72 P73 P74 P75 P76 P77 P80 (*2) P81 (*2) P82 (*2) P83 (*2) P84 (*2) P85 (*2) P86 (*2) P87 (*2) P90 (*1) P91 (*1) P92 (*1) P93 (*1) P94 (*1) P95 (*1) P96 (*1) P97 (*1) PB0 PB1 PB3 PB4 PB5 PB6 - - WAIT SCK, OPTRX0 SDA SI, SCL - - - MSK - - - - ADTRG - - - - KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7 TA0IN RXD2 INT0 INT1 INT2 INT3 OFF ON ON ON - - ON OFF ON - ON ON - ON ON - ON - OFF - ON - OFF ON - ON upon port read ON - OFF ON - ON - OFF ON ON ON ON ON ON OFF ON ON ON OFF ON OFF ON OFF OFF 91C820A-37 2006-01-31 TMP91C820A Input buffer state table (2/2) Input Function Name When the CPU is operating When When Used as Used as function Input Port Pin Input Buffer State In HALT mode In HALT mode(IDLE1/STOP) (IDLE2) Condition A (Note) Condition B (Note) When When When When When When Used Used as Used as Used as Used as Used as as Input function function function Input Port Input Port Port Pin Pin Pin ON ON ON OFF - - Port Name During Reset PB0 PB1 PB3 PB4 PB5 PB6 PC0 PC1 PC2 PC3 PC4 PC5 PE0-PE7 NMI/PS RESET (*1) AM0, AM1 X1, XT1 TA0IN RXD2 INT0 INT1 INT2 INT3 - RXD0 SCLK0, CTS0 - RXD1 SCLK1, CTS1 - - - OFF OFF ON ON ON ON - - OFF ON ON ON - ON - OFF ON - OFF ON - ON ON - ON - OFF OFF - ON - OFF ON - - - ON - ON - ON - IDLE1: ON, STOP: OFF *1: Port having a pull-up/pull-down resistor. *2: AIN input does not cause a current to flow through the buffer. ON: The buffer is always turned on. A current flows the input buffer if the input pin is not driven. OFF: The buffer is always turned off. -: No applicable Note: Condition A/B are as follows. SYSCR2 register setting 91C820A-38 2006-01-31 TMP91C820A Table 3.3.7 Output buffer state table (1/2) Output Buffer State Port Name Output Function Name When the CPU is operating When When Used as Used as function Output Pin Port ON upon external read In HALT mode (IDLE2) When Used as function Pin OFF When Used as Output Port In HALT mode (IDLE1/STOP) Condition A (Note) Condition B (Note) When When When When Used as Used as Used as Used as function Output function Output Pin Port Pin Port OFF During Reset P00-P07 P10-P17 P20-P27 P30-P37 D0-D7 D8-D15 A16-A23 A8-A15 OFF 8bit start: ON 16bit start: ON Built-in ROM start: OFF ON P40-P47 A0-A7 OFF ON ON ON PZ0 PZ1 PZ2 PZ3 P56 P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 RD WR HWR R/W, SRWE - CS0 CS1, SDCS CS2, CS2A CS3 EA24, CS2B EA25, CS2C CS2D, SRLB CS2E, SRUB SCK SO, SDA, OPTTX0 SCL CS2F CS2G CSEXA - VEECLK KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 OFF (*1) - - - - ON ON ON OFF ON ON ON OFF ON OFF - - - - ON ON OFF ON 91C820A-39 2006-01-31 TMP91C820A Output buffer state table (1/2) Output Buffer State Port Name Output Function Name When the CPU is operating When When Used as Used as function Output Pin Port ON - In HALT mode (IDLE2) When Used as function Pin ON - During Reset When Used as Output Port In HALT mode (IDLE1/STOP) Condition B (Note) Condition A (Note) When When When When Used as Used as Used as Used as function Output function Output Pin Port Pin Port OFF - PB0 PB1 PB3 PB4 PB5 PB6 PC0 PC1 PC2 PC3 PC4 PC5 PD0 PD1 PD2 PD3 PD4 PD6 PD7 PE0-7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 X2, XT2 TXD2 TA1OUT - - TA3OUT TB0OUT0 TXD0 - SCLK0 TXD1 - SCLK1 D1BSCP D2BLP D3BFR DLEBCD DOFFB ALARM, MLDALM MLDALM LD0-LD7 SDRAS SDCAS SDWE SDLDQM SDUDQM SDCKE ON - OFF ON - ON - OFF - ON - ON - ON - OFF - ON - ON ON ON OFF ON OFF OFF ON ON ON ON ON in self refresh cycle SDCLK - ON: The buffer is always turned on. OFF: The buffer is always turned off. -: No applicable OFF - - IDLE1: ON, STOP: output "H" level Note: Condition A/B are as follows. SYSCR2 register setting 91C820A-40 2006-01-31 TMP91C820A 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register SR A (Fixed) individual interrupt vector number is assigned to each interrupt. One of six (Variable) priority levels can be assigned to each maskable interrupt. The priority level of non-maskable interrupts is fixed at 7, the highest level. When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU. If multiple interrupts are generated simultaneously,the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority possible is level 7, used for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register 91C820A-41 2006-01-31 TMP91C820A Interrupt processing Micro DMA soft start request Yes Interrupt specified by micro DMA start vector? No Clear interrupt request flag Interrupt vector value "V" read Interrupt request F/F clear Data transfer by micro DMA General-purpose interrupt processing PUSH PC PUSH SR SR Count Count - 1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA transfer and interrupt (INTTC0 to INTTC3) PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 91C820A-42 2006-01-31 TMP91C820A 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps a and c and executes only steps b, d and e. a. The CPU reads the interrupt vector from the interrupt controller. If there are simultaneous interrupts set to same level, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: The smaller the vector value, the higher the priority level.) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (Pointed to by XSP). The CPU sets the value of the CPU's interrupt mask register b. c. d. e. The above processing time is 18 states (1.00 s at 36 MHz) as the best case (16-bit data bus width and 0 waits). When the CPU completed the interrupt processing, use the RETI instruction to return to the main routine. RETI restores the contents of the program counter and the status register from the stack and decrements the interrupt nesting counter INTNEST by 1. Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request is received for an interrupt with a priority level equal to or greater than the value set in the CPU interrupt mask register 91C820A-43 2006-01-31 TMP91C820A Table 3.4.1 TMP91C820A Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Maskable Nonmaskable Type Interrupt Source and Source of Micro DMA Request "Reset" or "SWI0" instruction "SWI1" instruction INTUNDEF: Illegal instruction or "SWI2" instruction "SWI3" instruction "SWI4" instruction "SWI5" instruction "SWI6" instruction "SWI7" instruction NMI pin Vector Vector Reference Value (V) Address 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H - - - 00A4H 00A8H 00ACH 00B0H 00B4H to 00FCH FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H - - - FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H to FFFFFCH Micro DMA Start Vector - - - - - - - - - - - 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H - - - - - - - 29H 2AH 2BH 2CH - to - INTWD: Watchdog timer (Micro DMA) INT0 pin INT1 pin INT2 pin INT3 pin INTALM0: ALM0 (8 kHz) INTALM1: ALM1 (512 Hz) INTALM2: ALM2 (64 Hz) INTALM3: ALM3 (2 Hz) INTALM4: ALM4 (1 Hz) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTRX0: Serial receives (Channel 0) INTTX0: Serial transmission (Channel 0) INTRX1: Serial receives (Channel 1) INTTX1: Serial transmission (Channel 1) INTAD: AD conversion end INTKEY: Key-on wakeup INTRTC: RTC (Alarm interrupt) INTSBI: SBI interrupt INTLCD: LCDC/LP pin INTP0: Protect 0 (WR to special SFR) INTP1: Protect 1 (WR to ROM) INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) Reserved Reserved Reserved INTRX2: Serial receive (Channel 2) INTTX2: Serial transmission (Channel 2) INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 1 (TB0RG1) (Reserved) to (Reserved) 91C820A-44 2006-01-31 TMP91C820A 3.4.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C820A supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the particular interrupt source. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU is a state of standby by HALT instruction, the requirement of micro DMA will be ignored (Pending). (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The four micro DMA channels allow micro DMA processing to be set for up to four types of interrupts at any one time. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. The data are automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the decremented counter reads other than 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the decremented reading is 0, the micro DMA transfer end interrupt (INTTC0 to INTTC3) passes from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA is disabled and micro DMA processing completes. If a micro DMA request is set for more than one channel at a time, the priority is not based on the interrupt priority level but on the channel number: the smaller the channel number the higher the priority (Channel 0 (High) Channel 3 (Low)). If an interrupt request is triggered for the interrupt source in use during the interval between the clearing of the micro DMA start vector and the next setting, general-purpose interrupt processing executes at the interrupt level set. Therefore, if only using the interrupt for starting the micro DMA (Not using the interrupts as a general-purpose interrupt), first set the interrupts level to 0 (Interrupt requests disabled). If using micro DMA and general-purpose interrupts together as described above, first set the level of the interrupt used to start micro DMA processing lower than all the other interrupt levels. In this case, the cause of general interrupt is limited to the edge interrupt. (Note) As with other maskable interrupts, the priority of the micro DMA transfer end interrupts is determined by the interrupt level and by the default priority. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91C820A-45 2006-01-31 TMP91C820A While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (The upper 8 bits of the 32 bits are not valid). Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One-word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are incremented, decremented, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) "Detailed description of the transfer mode register". As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 31 interrupts shown in the micro DMA start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 32 interrupts. Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even-numberd values). One state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Transfer source address Transfer destination address D0 to D15 Input Output Figure 3.4.2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (Gets next address code). If three or more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle. State 6: Dummy cycle (The address bus remains unchanged from state 5). States 7 to 8: Micro DMA write cycle. Note 1: If the source address area is an 8-bit bus, it is incremented by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is incremented by two states. Note 2: If the destination address area is an 8-bit bus, it is incremented by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is incremented by two states. 91C820A-46 2006-01-31 TMP91C820A (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C820A includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to each bit of DMAR register causes micro DMA once (If write "0" to each bit, micro DMA doesn't operate). At the end of transfer, the corresponding bit of the DMAR register which support the end channel are automatically cleared to 0. Only one channel can be set for DMA request at once. (Do not write 1 to plural bits) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. If read "1", micro DMA transfer isn't started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If execute soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writing to other bits by mistake. Symbol Name DMA request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 1 DMAR1 0 0 DMAR0 0 DMA request DMAR R/W (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form "LDC cr, r" can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0. DMA destination address register 0. DMA counter register 0. DMA mode register 0. Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3. DMA destination address register 3. DMA counter register 3. DMA mode register 3. 91C820A-47 2006-01-31 TMP91C820A (4) Detailed description of the transfer mode register 8 bits DMAM0 to 0 DMAM3 0 0 Mode Note: When setting a value in this register, write 0 to the upper three bits. Minimum Number of Execution States Execution Time (*) at fc = 36 MHz 8 states 444 ns Number of Transfer Bytes 000 (Fixed) 000 00 Byte transfer Mode Description Transfer destination address INC mode .................................................I/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Counter mode 12 sates 667 ns Transfer destination address DEC mode .................................................I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address INC mode .................................................Memory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode .................................................Memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Fixed address mode ......................................................... I/O to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. 8 states 444 ns 12 sates 667 ns 8 states 444 ns 12 sates 667 ns 8 states 444 ns 12 sates 667 ns 8 states 444 ns 12 sates 667 ns .....................For counting number of times interrupt is generated. DMASn DMASn + 1 DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. 5 sates 278 ns (*) For external 16-bit bus, 0 waits, word/4-byte transfer mode, transfer source/transfer destination addresses both have even-numbered values. Note: n: Corresponding micro DMA channels 0 to 3. DMADn+/DMASn+: Post increment (Increments register value after transfer). DMADn-/DMASn-: Post decrement (Decrements register value after transfer). The I/Os in the table mean fixed address; memory means increment and decrement addresses. Do not use undefined code, that is, codes other than those listed above for the transfer mode register. 91C820A-48 2006-01-31 TMP91C820A 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 36 interrupt channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (When micro DMA is set), when the micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing 0 to the clear bit in the interrupt priority setting register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). Six interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the CPU. The CPU compares the priority value 91C820A-49 2006-01-31 Interrupt controller Interrupt request F/F S R V = 20H V = 24H CPU 1 Interrupt mask F/F RESET Interrupt request NMI Q RESET interrupt vector read Priority setting register Priority encoder signal to CPU IFF2:0 3 3 1 7 3 INTRQ0 INTRQ2 to A INTWD Decoder B C Dn EI1 to 7 DI Interrupt level detect Dn + 1 Dn + 2 D Q CLR 6 6 Highest A priority B interrupt level select C Y1 Y2 Y3 Y4 Y5 Y6 if INTRQ2 to 0 IFF2 to 0 then 1. Interrupt request signal INT0 Reset Interrupt request F/F Dn + 3 SQ R Interrupt request F/F D0 D1 Interrupt vector read Micro DMA acknowledge 36 V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH Interrupt vector generator 1 2 3 4 5 6 7 INT1 INT2 INT3 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INTTA0 D2 D3 D4 D5 D6 D7 During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller 91C820A-50 Interrupt vector read V = A4H V = A8H V = ACH V = B0H Halt release RESET NMI 4 input OR 4 if IFF = 7 then 0 A B Micro DMA channel priority encoder 2 INT0 to INT3, INTKEY, INTRTC, INTALM Reserved INTRX2 INTTX2 INTTB00 INTTB01 Micro DMA start vector setting register Soft start 34 S Selector Micro DMA request D5 D4 D3 D2 D1 D0 DQ CLR 6 INTTC0 DMA0V DMA1V DMA2V DMA3V RESET 0 1 2 3 2 Micro DMA channel specification TMP91C820A 2006-01-31 TMP91C820A (1) Interrupt level setting registers Symbol Name INT0 and INTAD enable Address 7 IADC R 0 6 INTAD IADM2 0 INT2 I2M2 0 INTALM4 IA4M2 0 INTALM1 IA1M2 0 INTALM3 IA3M2 0 ITA1M2 0 ITA3M2 0 INTKEY IKM2 0 INTTX0 ITX0M2 0 5 IADM1 R/W 0 I2M1 R/W 0 IA4M1 R/W 0 IA1M1 R/W 0 IA3M1 R/W 0 ITA1M1 R/W 0 ITA3M1 R/W 0 IKM1 R/W 0 ITX0M1 R/W 0 4 IADM0 0 I2M0 0 IA4M0 0 IA1M0 0 IA3M0 0 ITA1M0 0 ITA3M0 0 IKM0 0 ITX0M0 0 3 I0C R 0 I1C R 0 I3C R 0 IA0C R 0 IA2C R 0 ITA0C R 0 ITA2C R 0 IRC R 0 IRX0C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INTALM0 IA0M2 0 INTALM2 IA2M2 0 ITA0M2 0 ITA2M2 0 INTRTC IRM2 0 INTRX0 IRX0M2 0 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 IA0M1 R/W 0 IA2M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 IRM1 R/W 0 IRX0M1 R/W 0 0 I0M0 0 I1M0 0 I3M0 0 IA0M0 0 IA2M0 0 ITA0M0 0 ITA2M0 0 IRM0 0 IRX0M0 0 INTE0AD 90H INTE12 INT1 and INT2 enable 91H I2C R 0 INTE3ALM4 INT3 and INTALM4 enable INTALM0 and INTALM1 enable INTALM2 and INTALM3 enable INTTA0 and INTTA1 enable INTTA2 and INTTA3 enable 92H IA4C R 0 IA1C R 0 IA3C R 0 ITA1C R 0 ITA3C R 0 IKC R 0 ITX0C R 0 INTEALM01 93H INTEALM23 94H INTTA1 (TMRA1) 95H INTTA0 (TMRA0) INTETA01 INTTA3 (TMRA3) 96H INTTA2 (TMRA2) INTETA23 INTRTC and INTERTCKEY INTKEY enable Interrupt enable serial 0 97H INTES0 98H Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91C820A-51 2006-01-31 TMP91C820A Symbol Name INTRX1 and INTTX1 enable Address 7 ITXT1C R 0 ILCD1C R 0 ITC1C R 0 ITC3C R 0 IP1C R 0 ITX2C R 0 ITB1C R 0 6 INTTX1 ITX1M2 0 INTLCD ILCDM2 0 INTTC1 ITC1M2 0 INTTC3 ITC3M2 0 INTP1 IP1M2 0 INTTX2 ITX2M2 0 INTTB01 ITB1M2 0 5 ITX1M1 R/W 0 ILCDM1 R/W 0 ITC1M1 R/W 0 ITC3M1 R/W 0 IP1M1 R/W 0 ITX2M1 R/W 0 ITB1M1 R/W 0 4 ITX1M0 0 ILCDM0 0 ITC1M0 0 ITC3M0 0 IP1M0 0 ITX2M0 0 ITB1M0 0 3 IRX1C R 0 ISBIC R 0 ITC0C R 0 ITC2C R 0 IP0C R 0 IRX2C R 0 ITB0C R 0 2 INTRX1 IRX1M2 0 INTSBI ISBIM2 0 INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 INTP0 IP0M2 0 INTRX2 IRX2M2 0 INTTB00 ITB0M2 0 1 IRX1M1 R/W 0 ISBIM1 R/W 0 ITC0M1 R/W 0 ITC2M1 R/W 0 IP0M1 R/W 0 IRX2M1 R/W 0 ITB0M1 R/W 0 0 IRX1M0 0 ISBIM0 0 ITC0M0 0 ITC2M0 0 IP0M0 0 IRX2M0 0 ITB0M0 0 INTES1 99H INTSBI and INTES2LCD INTLCD enable INTTC0 and INTTC1 enable INTTC2 and INTTC3 enable INTP0 and INTP1 enable INTRX2 and INTTX2 enable INTTB00 and INTTB01 enable 9AH INTETC01 9BH INTETC23 9CH INTEP01 9DH INTES3 A0H INTETB0 A1H Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91C820A-52 2006-01-31 TMP91C820A (2) External interrupt control Symbol Name Address 7 - 8CH IIMC Interrupt input mode control 0 Always write "0". (Prohibit RMW) 6 - 0 Always write "0". 5 I3EDGE 0 4 I2EDGE W 3 I1EDGE 0 2 I0EDGE 0 1 I0LE 0 0 NMIREE 0 1: Operates even on rising/ falling edge of NMI 0 INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0: INT0 edge 0: Rising 0: Rising 0: Rising 0: Rising mode 1: Falling 1: Falling 1: Falling 1: Falling 1: INT0 level mode INT0 level enable 0 1 0 1 edge detect INT H level INT INT request generation at falling edge INT request generation at rising/falling edge NMI rising edge enable (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1 to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH: Clears interrupt request flag INT0. Symbol Name Address Interrupt clear control 88H 0 (Prohibit RMW) 0 0 7 6 5 CLRV5 4 CLRV4 3 CLRV3 W 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 INTCLR Interrupt vector (4) Micro DMA start vector registers This register assigns micro DMA processing to an interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel; the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number. (Micro DMA chaining.) 91C820A-53 2006-01-31 TMP91C820A Symbol Name DMA0 start vector Address 7 6 5 DMA0V5 0 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA0 start vector DMA0V 80H R/W DMA1 start vector DMA1V DMA1 start vector 81H DMA1V5 0 DMA2 start vector DMA2V5 0 DMA3 start vector DMA3V5 0 R/W DMA2 start vector DMA2V 82H R/W DMA3 start vector DMA3V 83H R/W (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches zero after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to 1 specifies a burst. Symbol Name DMA software request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 R/W 0 DMAB3 2 DMAR2 R/W 0 DMAB2 R/W 0 1 DMAR1 R/W 0 DMAB1 0 0 DMAR0 R/W 0 DMAB0 0 DMAR 1: DMA software request DMAB DMA burst register 8AH 0 1: DMA burst request 91C820A-54 2006-01-31 TMP91C820A (6) Notes The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interrupt vector address FFFF08H. To avoid the above problem, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1 instructions (ex. "NOP" x 1 time). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register ;INT0 level mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches interrupt input mode from level mode to edge mode. ; Wait EI instruction LD (INTCLR), 0AH ; Clears interrupt request flag. NOP EI INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input changes from high to low after an interrupt request has been generated in level mode. (H L) INTRX: Instructions which read the receive buffer. 91C820A-55 2006-01-31 TMP91C820A 3.5 Port Functions The TMP91C820A features 126-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 and Table 3.5.2 list the functions of each port pin. Table 3.5.3, Table 3.5.4 and Table 3.5.5 list I/O registers and their specifications. Table 3.5.1 Port Functions (1/2) (R: PU = with programmable pull-up resistor) (U = with pull-up resistor) Port Name Port 0 Port 1 Port 2 Port 3 Port 4 Port Z Pin Name P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 PZ0 PZ1 PZ2 PZ3 Number of Pins 8 8 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 Direction I/O I/O I/O I/O I/O Output Output I/O I/O I/O Output Output Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O Input Input Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - - - PU PU PU - - - - - - - - - - - - - - - - - U - - - - - - - - - - - - - Direction Setting Unit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Name for Built-in Function D0 to D7 D8 to D15 A16 to A23 A8 to A15 A0 to A7 RD WR HWR R / W , SRWE WAIT CS0 CS1 , SDCS CS2 , CS2A CS3 Port 5 Port 6 P56 P60 P61 P62 P63 P64 P65 P66 P67 EA24, CS2B EA25, CS2C CS2C , SRLB CS2E , SRUB Port 7 P70 P71 P72 P73 P74 P75 P76 P77 SCK, OPTRX0 SO, SDA , OPTTX0 SI/SCL CS2F CS2G CSEXA MSK VEECLK AN0 to AN7, ADTRG (P83) KI0 to KI7 KO0 to KO7 TA0IN, TXD2 TA1OUT, RXD2 INT0 INT1 INT2, TA3OUT INT3, TB0OUT0 TXD0 RXD0 SCLK0, CTS0 TXD1 RXD1 SCLK1, CTS1 Port 8 Port 9 Port A Port B P80 to P87 P90 to P97 PA0 to PA7 PB0 PB1 PB3 PB4 PB5 PB6 Port C PC0 PC1 PC2 PC3 PC4 PC5 91C820A-56 2006-01-31 TMP91C820A Table 3.5.2 Port Functions (2/2) (R: PU = with programmable pull-up resistor) (U = with pull-up resistor) Port Name Port D Pin Name PD0 PD1 PD2 PD3 PD4 PD6 PD7 Number of Pins 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 Direction Output Output Output Output Output Output Output I/O Output Output Output Output Output Output Output Output R - - - - - - - - - - - - - - - - Direction Setting Unit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Pin Name for Built-in Function D1BSCP D2BLP D3BFR DLEBCD DOFFB ALARM , MLDALM MLDALM LD0 to LD7 SDRAS SDCAS SDWE Port E Port F PD0 to PD7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 SDLDQM SDUDQM SDCKE SDCLK 91C820A-57 2006-01-31 TMP91C820A Table 3.5.3 I/O Registers and Specifications (1/3) Port Port 0 Pin Name P00 to P07 Input port Output port Specification I/O Register Pn X X X X X X X X X X X X X X X X X X X 0 1 X X X X 0 1 X 0 1 X X X X X X X X X X X X X X X None 0 0 1 1 0 1 0 0 1 0 0 0 1 1 X 1 X 1 1 X 1 X 1 X 1 X 0 0 0 1 0 1 0 0 1 0 1 0 1 0 1 None None PnCR 0 1 X 0 1 0 0 1 1 0 1 1 0 1 1 PnFC PnFC2 None 0 0 1 X 0 1 X 0 1 X 0 1 0 1 0 1 0 0 0 1 1 1 None None None None None None D0 to D7 bus Port 1 P10 to P17 Input port Output port D8 to D15 bus Port 2 P20 to P27 Input port Output port A16 to A23 output Port 3 P30 to P47 Input port Output port A8 to A15 output Port 4 P30 to P47 Input port Output port A0 to A7 output Port Z PZ0 PZ1 PZ2, PZ3 Output port RD output Output port WR output Input port (without PU) Input port (with PU) Output port PZ2 PZ3 Port 5 P56 HWR output R/W output SRWE output Input port (without PU) Input port (with PU) Output port WAIT input (without PU) WAIT input (with PU) Port 6 P60 to P67 P60 P61 P62 P63 P64 P65 P66 P67 Output port CS0 output CS1 output SDCS output CS2 output CS2A output CS3 output EA24 output CS2B output EA25 output CS2C output SRLB output CS2D output SRUB output CS2E output X: Don't care 91C820A-58 2006-01-31 TMP91C820A Table 3.5.4 I/O Registers and Specifications (2/3) Port Port 7 Pin Name P70 to P77 P70 Input port Output port SCK input SCK output Specification I/O Register Pn X X X X PnCR 0 1 0 1 0 0 1 1 1 0 0 1 1 1 1 0 1 PnFC PnFC2 0 0 0 1 X 0 1 1 X 0 0 1 X X X 0 1 1 1 1 0 0 None 0 0 0 0 1 0 0 0 1 OPTRX0 input P71 SDA input SDA output SO output OPTTX0 output P72 SI input SCL input SCL output P73 P74 P75 P76 P77 Port 8 P80 to P87 P83 Port 9 Port A P90 to P97 PA0 to PA7 CS2F output CS2G output CSEXA output (Note 1) (Note 2) (Note 1) 1 X X X 1 X X (Note 2) X X X X MSK input VEECLK output Input port AN0 to AN7 input ADTRG input (Note 3) X X X (Note 4) (Note 5) X X X X X X X X X X 0 1 0 1 1 0 0 0 0 1 0 1 None 0 1 0 None 0 1 0 0 0 1 1 0 1 1 1 1 1 1 None Input port KI0 to KI7 input Output port KO0 to KO7 output (CMOS) KO0 to KO7 output (Open drain) None None Port B PB0 to PB6 PB0 PB1 PB3 PB4 PB5 PB6 Input port Output port TA0IN input TXD2 output TA1OUT output RXD2 input INT0 input INT1 input INT2 input TA3OUT INT3 input TB0OUT0 (Note 1) (Note 1) X X X X X 0 1 0 1 X: Don't care 91C820A-59 2006-01-31 TMP91C820A Table 3.5.5 I/O Registers and Specifications (3/3) Port Port C Pin Name PC0 to PC5 PC0 PC1 PC2 Input port Output port Specification I/O Register Pn X X PnCR 0 1 1 0 0 1 0 1 0 0 1 0 PnFC PnFC2 0 0 1 None 0 1 0 1 None 0 1 0 0 1 1 1 TXD0 output RXD0 input SCLK0 input SCLK0 output CTS0 input (Note 1) (Note 1, 6) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) 1 1 1 1 1 1 1 1 1 1 X X X X X X 1 0 X X X X X X X X X X X X PC3 PC4 PC5 TXD1 output RXD1 input SCLK1 input SCLK1 output CTS1 input Port D PD0 to PD7 PD0 PD1 PD2 PD3 PD4 PD6 PD7 Output port D1BSCP output D2BLP output D3BFR output DLEBCD output DOFFB output ALARM output MLDALM output None None 1 1 1 1 1 MLDALM output Input port Output port LD0 to LD7 output Port E PE0 to PE7 0 1 1 0 0 1 0 1 1 1 1 1 1 1 Port F PF0 to PF7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 Output port SDRAS output SDCAS output SDWE output None SDLDQM output SDUDQM output SDCKE output SDCLK output X: Don't care Note 1: As for input ports of SIO1 to SIO3: (OPTTX0, OPTRX0, TXD0, RXD0, SCLK0, CTS0 , TXD1, RXD1, SCLK1, CTS1 , TXD2, RXD2), logical selection for output data or input data is determined by the output latch register Pn of each port. Note 2: When P71/P72 are used as SDA/SCL open-drain outputs, P70DE 91C820A-60 2006-01-31 TMP91C820A 3.5.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P0CR. Resetting resets all bits of the output latch P0, the control register P0CR to 0 and sets port 0 to input mode. In addition to functioning as a general-purpose I/O port, port 0 can also function as an data bus (D0 to D7). When external memory is accesed, the port automatically functions as the data bus (D0 to D7) and all bits of P0CR are cleared to 0. Reset Direction control (on bit basis) P0CR write A S P00 to P07 (D0 to D7) External access External access (Data write) Internal data bus Output latch P0 write D0 to D7 Selector Output buffer B P0 read External access (Data read) Figure 3.5.1 Port 0 Port 0 Register 7 P0 (0000H) Bit symbol Read/Write After reset P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Data from external port (Output latch register is cleared to 0.) Port 0 Control Register 7 P0CR (0002H) Bit symbol Read/Write After reset Function 0 P07C 6 P06C 0 5 P05C 0 4 P04C W 0 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 Port 0 input/output settings 0: Input 1:Output Note 1: Read-modify-write is prohibited for P0CR. Note 2: When functioning as a data bus (D0 to D7), P0CR is cleared to 0. Figure 3.5.2 Register for Port 0 91C820A-61 2006-01-31 TMP91C820A 3.5.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR and the function register P1FC. Resetting resets all bits of the output latch P1, the control register P1CR and the function register P1FC to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an data bus (D8 to D15). AM1 AM0 0 0 1 1 0 1 0 1 P1xF 0 1 - 0 Function Setting after Reset is Released Input port Data bus (D8 to D15) Don't use this setting Input port Reset Direction control (on bit basis) P1CR write Function control (on bit basis) Internal data bus P1FC write Output latch P1 write D8 to D15 A S Port 1 P10 to P17 (D8 to D15) External access (Data write) Selector Output buffer B P1 read External access (Data read) Figure 3.5.3 Port 1 91C820A-62 2006-01-31 TMP91C820A Port 1 Register 7 P1 P0 (0001H) (0000H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) Port 1 Control Register 7 P1CR (0004H) Bit symbol Read/Write After reset Function 0 P17C 6 P16C 0 5 P15C 0 4 P14C W 0 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 Port 1 function settings Port 1 Function Register 7 P1FC (0005H) Bit symbol Read/Write After reset (Note3) Function 0/1 P17F 6 P16F 0/1 5 P15F 0/1 4 P14F W 0/1 3 P13F 0/1 2 P12F 0/1 1 P11F 0/1 0 P10F 0/1 Port 1 function settings Port 1 function settings Note 1: Read-modify-write is prohibited for P1CR and P1FC. Note 2: Figure 3.5.4 Register for Port 1 91C820A-63 2006-01-31 TMP91C820A 3.5.3 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P2CR and the function register P2FC. In addition to functioning as a general-purpose I/O port, port 2 can also function as an address bus (A16 to A23). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 2 to the following function pins. AM1 AM0 P2xC 0 0 1 1 0 1 0 1 1 1 - 0 P2xF Function Setting after Reset is Released 1 1 - 0 Address bus (A16 to A23) Address bus (A16 to A23) Don't use this setting Input port Reset Internal address bus A16 to A23 Direction control (on bit basis) P2CR write Function control (on bits basis) Internal data bus S Selector P2FC write B P20 to P27 (A16 to A23) Output latch P2 write A Output buffer P2 read Figure 3.5.5 Port 2 91C820A-64 2006-01-31 TMP91C820A Port 2 Register 7 P2 P0 (0006H) (0000H) Bit symbol Read/Write After reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Data from external port (Output latch register is cleared to 0.) Port 2 Control Register 7 P2CR (0008H) Bit symbol Read/Write After reset (Note3) Function 0/1 P27C 6 P26C 0/1 5 P25C 0/1 4 P24C W 0/1 3 P23C 0/1 2 P22C 0/1 1 P21C 0/1 0 P20C 0/1 Port 2 function settings Port 2 Function Register P2FC (0009H) 7 Bit symbol Read/Write After reset (Note3) Function 0/1 P27F 6 P26F 0/1 5 P25F 0/1 4 P24F W 0/1 3 P23F 0/1 2 P22F 0/1 1 P21F 0/1 0 P20F 0/1 Port 2 function settings Note 1: Read-modify-write is prohibited for P2CR and P2FC. Note 2: Port 2 function settings P2FC Figure 3.5.6 Register for Port 2 91C820A-65 2006-01-31 TMP91C820A 3.5.4 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P3CR and the function register P3FC. In addition to functioning as a general-purpose I/O port, port 3 can also function as an address bus (A8 to A15). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 3 to the following function pins. AM1 AM0 P3xC 0 0 1 1 0 0 0 1 1 1 - 0 P3xF Function Setting after Reset is Released 1 1 - 0 Address bus (A8 to A15) Address bus (A8 to A15) Don't use this setting Input port Reset Internal address bus A8 to A15 Direction control (on bit basis) P3CR write Function control (on bit basis) Internal data bus S Selector P3FC write B P30 to P37 (A8 to A15) Output latch P3 write A Output buffer P3 read Figure 3.5.7 Port 3 91C820A-66 2006-01-31 TMP91C820A Port 3 Register 7 P3 P0 (0007H) (0000H) Bit symbol Read/Write After reset P37 6 P36 5 P35 4 P34 R/W 3 P33 2 P32 1 P31 0 P30 Data from external port (Output latch register is cleared to 0.) Port 3 Control Register 7 P3CR (000AH) Bit symbol Read/Write After reset (Note3) Function 0/1 P37C 6 P36C 0/1 5 P35C 0/1 4 P34C W 0/1 3 P33C 0/1 2 P32C 0/1 1 P31C 0/1 0 P30C 0/1 Port 3 function settings Port 3 Function Register P3FC (000BH) 7 Bit symbol Read/Write After reset (Note3) Function 0/1 P37F 6 P36F 0/1 5 P35F 0/1 4 P34F W 0/1 3 P33F 0/1 2 P32F 0/1 1 P31F 0/1 0 P30F 0/1 Port 3 function settings Note 1: Read-modify-write is prohibited for P3CR and P3FC. Note 2: Port 3 function settings P3FC Figure 3.5.8 Register for Port 3 91C820A-67 2006-01-31 TMP91C820A 3.5.5 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P4CR and the function register P4FC. In addition to functioning as a general-purpose I/O port, port 4 can also function as an address bus (A0 to A7). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 4 to the following function pins. AM1 AM0 P4xC 0 0 1 1 0 1 0 1 1 1 - 0 P4xF Function Setting after Reset is Released 1 1 - 0 Address bus (A0 to A7) Address bus (A0 to A7) Don't use this setting Input port Reset Internal address bus A0 to A7 Direction control (on bit basis) P4CR write Function control (on bit basis) Internal data bus S Selector P4FC write B P40 to P47 (A0 to A7) Output latch P4 write A Output buffer P4 read Figure 3.5.9 Port 4 91C820A-68 2006-01-31 TMP91C820A Port 4 Register 7 P4 P0 (000CH) (0000H) Bit symbol Read/Write After reset P47 6 P46 5 P45 4 P44 R/W 3 P43 2 P42 1 P41 0 P40 Data from external port (Output latch register is cleared to 0.) Port 4 Control Register 7 P4CR (000EH) Bit symbol Read/Write After reset (Note3) Function 0/1 P47C 6 P46C 0/1 5 P45C 0/1 4 P44C W 0/1 3 P43C 0/1 2 P42C 0/1 1 P41C 0/1 0 P40C 0/1 Port 4 function settings Port 4 Function Register P4FC (000FH) 7 Bit symbol Read/Write After reset (Note3) Function 0/1 P47F 6 P46F 0/1 5 P45F 0/1 4 P44F W 0/1 3 P43F 0/1 2 P42F 0/1 1 P41F 0/1 0 P40F 0/1 Port 4 function settings Note 1: Read-modify-write is prohibited for P4CR and P4FC. Note 2: Port 4 function settings P4FC Figure 3.5.10 Register for Port 4 91C820A-69 2006-01-31 TMP91C820A 3.5.6 Port Z (PZ0 to PZ3) Port Z is an 4-bit general-purpose I/O port (P50 and P51 are used for output only). I/O is set using control register PZCR and PZFC. Resetting resets all bits of the output latch PZ to 1. In addition to functioning as a general-purpose I/O port, port Z also functions as I/O for the CPU's control/status signal. When PZ0 pin is defined as RD strobe signal output mode ( 1 1 - 0 PZ0 function RD pin RD pin AM1 AM0 0 0 1 1 0 1 0 1 PZ1 function WR pin WR pin Don't use this setting Output port Don't use this setting Output port Reset Function control (on bit basis) PZFC write Internal data bus S latch B PZ write Selector Output A PZ0 ( RD ) Output buffer PZ read RD Internal address area Figure 3.5.11 Port Z (PZ0) 91C820A-70 2006-01-31 TMP91C820A Reset Function control (on bit basis) PZFC write Internal data bus S latch B PZ write Selector Output A PZ1 ( WR ) Output buffer PZ read WR Internal address area Reset Direction control (on bit basis) PZCR write Function conrtol Internal data bus (on bit basis) PZFC write S Selector P-ch A B (Programmable pull up) S Output latch PZ write PZ2 ( HWR ) Output buffer HWR PZ read Figure 3.5.12 Port Z (PZ1, PZ2) 91C820A-71 2006-01-31 TMP91C820A Reset Direction control (on bit basis) PZCR write Function conrtol (on bit basis) Internal data bus PZFC write S Selector S Output latch PZ write A PZ3 ( R / W , SRWE ) Output buffer B C P-ch (Programmable pull up) R/W SRWE P5 read Figure 3.5.13 Port Z (PZ3) 91C820A-72 2006-01-31 TMP91C820A Port Z Register 7 PZ (007DH) Bit symbol Read/Write After reset Function 6 5 4 3 PZ3 2 PZ2 R/W 1 PZ1 1 - 0 PZ0 1 - Data form external port (Note 1) 0(Output latch register): Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON Port Z Control Register 7 PZCR (007EH) Bit symbol Read/Write After reset Function 6 5 4 3 PZ3C W 0 0: Input 2 PZ2C 0 1: Output 1 0 Port Z Function Register 7 PZFC (007FH) Bit symbol Read/Write After reset Function 6 5 4 3 PZ3F 0 0: Port 1: R / W , SRWE 2 PZ2F W 0 0: Port 1: HWR 1 PZ1F 0 0: Port 1: WR 0 PZ0F 0 0: Port 1: RD Note 1: Output latch register is set to 1. R / W , SRWE setting Note 2: Read-modify-write is prohibited for PZ0 ( RD ) function setting 1 Output SRWE 0 Output Prohibit this setting 1 Output RD PZ1 ( WR ) function setting 0 Output WR 1 Output HWR setting PZFC 1 PZCR Figure 3.5.14 Register for Port Z 91C820A-73 2006-01-31 TMP91C820A 3.5.7 Port 5 (P56) Port 5 is an 1-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to P1. In addition to functioning as a general-purpose I/O port, port 5 also functions as I/O for the CPU's control/status signal. Resetting initializes P56 pins to input mode with pull-up resistor. Reset Direction control (on bit basis) P5CR write Internal data bus P-ch (Programmable pull up) P56 ( WAIT ) S Output latch P5 write Output buffer Internal WAIT P5 read Figure 3.5.15 Port 5 (P56) 91C820A-74 2006-01-31 TMP91C820A Port 5 Register 7 P5 (000DH) Bit symbol Read/Write After reset 6 P56 R/W Data from external port (Output latch register is set to 1.) 5 4 3 2 1 0 Function 0(Output latch register): Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON Port 5 Control Register 7 P5CR (0010H) Bit symbol Read/Write After reset Function Note: 6 P56C W 0 0: Input 1: Output 5 4 3 2 1 0 When the P53/WAIT pin is to be use as the WAIT pin, P5CR Figure 3.5.16 Register for Port 5 91C820A-75 2006-01-31 TMP91C820A 3.5.8 Port 6 (P60 to P67) Port 60 to 67 are 8-bit output ports. Resetting sets output latch of P62 to 0 and output latches of P60 to P61 and P63 to P67 are set to 1. Port 6 also function as chip-select output ( CS0 to CS3 ), extend address output (EA24, EA25), extend chip-select output ( CS2A , CS2B , CS2C , CS2D , CS2E ), SRAM byte control output ( SRUB , SRLB ), and SDRAM chip-select output ( SDCS ). Writing 1 in the corresponding bit of P6FC, P6FC2 enables the respective functions. Resetting reset the P6FC and P6FC2 to 0, and sets all bits to output ports. Reset Function control 2 (on bit basis) P6FC2 write Function control (on bit basis) P6FC write S Output lacth P6 write A B C Selector P60 ( CS0 ) P61 ( CS1 , SDCS ) P62 ( CS2 , CS2A ) P63 ( CS3 ) P64 (EA24, CS2B ) P65 (EA25, CS2C ) P66 ( SRLB , CS2D ) P67 ( SRUB , CS2E ) Internal data bus SDCS , CS2A , CS2B , CS2C , CS2D , CS2E P6 read CS0 , CS1 , CS2 , CS3 , EA24, EA25, SRLB , SRUB Figure 3.5.17 Port 6 Port 6 Register 7 P6 (0012H) Bit symbol Read/Write After reset 1 P67 6 P66 1 5 P65 1 4 P64 R/W 1 3 P63 1 2 P62 0 1 P61 1 0 P60 1 Port 6 Function Register 7 P6FC (0015H) Bit symbol Read/Write After reset Function 0: Port 1: SRUB P67F 6 P66F 5 P65F 4 P64F W 0 3 P63F 2 P62F 1 P61F 0 P60F 0: Port 1: SRLB 0: Port 1: EA25 0: Port 1: EA24 0: Port 1: CS3 0: Port 1: CS2 0: Port 1: CS1 0: Port 1: CS0 Port 6 Function Register 2 7 P6FC2 (001BH) Bit symbol Read/Write After reset Function P67F2 6 P66F2 5 P65F2 4 P64F2 W 0 3 - 2 P62F2 1 P61F2 0 - 0: Always write "0". 0: Always write "0". Note: Read-modify-write is prohibited for P6FC and P6FC2. Figure 3.5.18 Register for Port 6 91C820A-76 2006-01-31 TMP91C820A 3.5.9 Port 7 (P70 to P77) Port 7 is an 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets port 7 to input port and all bits of output latch to 1. In addition to functioning as a general-purpose I/O port, port 7 also functions as follows. 1. Input/output function for serial bus interface (SCK, SO/SDA, SI/SCL) 2. 3. 4. Input/output function for IrDA (OPTRX0, OPTTX0) Extend chip-select output ( CS2F , CS2G , CSEXA ) Clock control function for voltage booster of external LCD driver (MSK, VEECLK) Writing 1 in the corresponding bit of P7FC, P7FC2 enables the respective functions. Resetting resets the P7FC, P7FC2 to 0, and sets all bits to input ports. (1) Port 70 (SCK, OPTRX0) Port 70 is a general-purpose I/O port. It is also used as SCK (Clock signal for SIO mode) and OPTRX0 (Receive input for IrDA mode of SIO0). Used as OPTRX0, it is possible to logical invert by P7 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) Internal data bus P7FC write S Output latch P7 write SCK output SB Selector P7 read Function control 2 (on bit basis) P7FC2 write RXD0 (to SIO0) A SCK input Logical invert SB Selector A RXD0PC1 (from PORTC1) A S P70 (SCK, OPTRX0) Selector B Figure 3.5.19 Port 70 91C820A-77 2006-01-31 TMP91C820A (2) Port 71 (SO/SDA/OPTTX0) Port 71 is a general-purpose I/O port. It is also used as SDA (Data input for I2C bus mode), SO (Data output for SIO mode) for serial bus interface and OPTTX0 (Transmit output for IrDA mode of SIO0). Used as OPTTX0, it is possible to logical invert by P7 Reset Function control 2 (on bit basis) P7FC2 write Direction control (on bit basis) Internal data bus P7CR write Function control (on bit basis) P7FC write S Output latch P7 write SO output A S P71(SO/SDA, OPTTX0) Open-drain possible: P7ODE Selector B C TXD0 output Logical invert SB Selector P7 read SDA input A Figure 3.5.20 Port 71 91C820A-78 2006-01-31 TMP91C820A (3) Port 72 (SI/SCL) Port 72 is a general-purpose I/O port. It is also used as SI (Data input for SIO mode), SCL (Clock input/output for I2C bus mode) for serial bus interface. Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write S Output latch P7 write SCL output Internal data bus A S P72 (SI/SCL) Open-drain possible: P7ODE Selector B SB Selector P7 read SI input SCL input A Figure 3.5.21 Port 72 91C820A-79 2006-01-31 TMP91C820A (4) Port 73 ( CS2F ), 74 ( CS2G ), 75 ( CSEXA ) Port 73 to 75 are general-purpose I/O ports. These are also used as control signal for sequential mask ROM and extend chip-select output. Reset Function control 2 (on bit basis) P7FC2 write Direction control (on bit basis) Internal data bus P7CR write Funtcion control (on bit basis) P7FC write S Output latch P7 write CS2F , CS2G , CSEXA A S P73 ( CS2F ), P74 ( CS2G ), P75 ( CSEXA ) Selector B SB Selector P7 read A Figure 3.5.22 Port 73, 74, 75 91C820A-80 2006-01-31 TMP91C820A (5) Port 76 (MSK), 77 (VEECLK) Port 76 and 77 are general-purpose I/O ports. These are also used as clock control function for voltage booster of external LCD driver. MSK pin (P76) is an input pin from external LCD driver, clock output from VEECLK pin is controlled by state of this pin. Logic of this pin is controlled with P7FC Reset Direction control (on bit basis) P7CR write Internal data bus S Output latch P7 write S P7 read P76 (MSK) B Selector A Function control (on bit basis) P7FC write fs clock VEECLK Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Internal data bus S Output latch A P7 write S P77 (VEECLK) Selector B S B P7 read Selector A Figure 3.5.23 Port 76, 77 91C820A-81 2006-01-31 TMP91C820A Port 7 Register 7 P7 (0013H) Bit symbol Read/Write After reset P77 6 P76 5 P75 4 P74 R/W 3 P73 2 P72 1 P71 0 P70 Data from external port (Output latch register is set to 1.) Port 7 Control Register 7 P7CR (0016H) Bit symbol Read/Write After reset Function 0 P77C 6 P76C 0 5 P75C 0 0: Input 4 P74C W 0 3 P73C 0 1: Output 2 P72C 0 1 P71C 0 0 P70C 0 Port 7 Function Register 7 P7FC (0017H) Bit symbol Read/Write After reset Function 0:Port P77F 6 P76F 5 P75F 4 P74F W 0 3 P73F 2 P72F 1 P71F 0 P70F MSK 0: Enable 1: Enable 0: Port 0: Port 0: Port 0: Port 1: SCL/SI 0: Port 1: SDA/SO 0: Port 1: SCK 1:VEECLK select Port 7 Function Register 2 7 P7FC2 (001CH) Bit symbol Read/Write After reset Function Always write "0". 6 - 5 P75F2 4 P74F2 W 0 3 P73F2 2 - 1 P71F2 0 P70F2 - Always write "0". 0: 0: 0: Always write 0: SIO0/RXD0 Pin select 0: RXD0(PC1) 1: OPTRX0 (P70) Port 7 ODE Register 7 P7ODE (001FH) Bit symbol Read/Write After reset Function 0 Always write "0". 6 - W 0 5 4 3 2 ODEP72 W 0 0: 3 states 1: Open drain 1 ODEP71 0 0 - Note: Read-modify-write is prohibited for P7CR, P7FC, P7FC2 and P7ODE. Figure 3.5.24 Register for Port 7 91C820A-82 2006-01-31 TMP91C820A 3.5.10 Port 8 (P80 to P87) Port 8 is an 8-bit input port and can also be used as the analog input pins for the internal AD converter. P83 can also be used as ADTRG pin for the AD converter. Port 8 Internal data bus Port 8 read P80 to P87 (AN0 to AN7) Conversion result register AD converter Channel selector AD read ADTRG (for P83 only) Figure 3.5.25 Port 8 Port 8 Register 7 P8 (0018H) Bit symbol Read/Write After reset P87 6 P86 5 P85 4 P84 R 3 P83 2 P82 1 P81 0 P80 Data from external port Note: The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register ADMOD1. Figure 3.5.26 Register for Port 8 91C820A-83 2006-01-31 TMP91C820A 3.5.11 Port 9 (P90 to P97) Port 90 to 97 are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O port, port 90 to 97 can also key-on wakeup function as keyboard interface. The various functions can each be enabled by writing a 1 to the corresponding bit of the port 9 function register (P9FC). Resetting resets all bits of the register P9FC to 0 and sets all pins to be input port. INTKEY Internal data bus Rising edge detection P90 to P97 8-OR Reset Key-on enable (on bit basis) P9FC write P90 to P97 (KI0 to KI7) P9 read Pull-up resistor Figure 3.5.27 Port 9 When P9FC = 1, if either of input of KI0 to KI7 pins falls down, INTKEY interrupt is generated. INTKEY interrupt can be used to release all HALT mode. Port 9 Register 7 P9 (0019H) Bit symbol Read/Write After reset P97 6 P96 5 P95 4 P94 R 3 P93 2 P92 1 P91 0 P90 Data from external port Port 9 Function Register 7 P9FC (001DH) Bit symbol Read/Write After reset Function 0 P97F 6 P96F 0 5 P95F 0 4 P94F W 0 3 P93F 0 2 P92F 0 1 P91F 0 0 P90F 0 0: Key-in disable 1: Key-in enable Key-in of port 9 Disable Enable Note: Read-modify-write is prohibited for the registers P9FC. 0 1 Figure 3.5.28 Register for Port 9 91C820A-84 2006-01-31 TMP91C820A 3.5.12 Port A (PA0 to PA7) Port PA0 to PA7 are 8-bit output ports, and also used key board interface pin KO0 to KO7 which can set open-drain output buffer. Writing 1 in the corresponding bit of the port A function register (PAFC) enable the open-drain output. Resetting reset bits of the registers PA to 1 and PAFC to 0, and all pin outputs 1. Reset Output buffer set Internal data bus PAFC write S Output latch PA write PA read Programmable open drain PA0 to PA7 (KO0 to KO7) Figure 3.5.29 Port A Port A Register 7 PA (001EH) Bit symbol Read/Write After reset 1 PA7 6 PA6 1 5 PA5 1 4 PA4 R/W 1 3 PA3 1 2 PA2 1 1 PA1 1 0 PA0 1 Port A Function Register 7 PAFC (0021H) Bit symbol Read/Write After reset Function Note: 0 PA7F 6 PA6F 0 5 PA5F 0 4 PA4F W 0 0: CMOS output 3 PA3F 0 1: Open drain 2 PA2F 0 1 PA1F 0 0 PA0F 0 Read-modify-write is prohibited for PAFC. Figure 3.5.30 Register for Port A 91C820A-85 2006-01-31 TMP91C820A 3.5.13 Port B (PB0 to PB6) Port B is a 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port B to be an input port. In addition to functioning as a general-purpose I/O port, port B can also function as I/O pin for timers (TA0IN, TA1OUT, TA3OUT, TB0OUT0), input pin for external interruption (INT0 to INT3), and I/O for serial channels 2 (TXD2, RXD2). Above setting is used the function register PBFC and PBFC2. Edge select of external interruption establishes it with IIMC register, which there is in interruption controller. (1) PB0 (TA0IN, TXD2) As well as functioning as I/O port pins, port B0 can also function as serial channel TXD output pins. In case of use TXD2, it is possible to logical invert by setting the register PB Reset Direction control (on bits basis) PBCR write Function control (on bit basis) PBFC write S Output latch PB write TXD2 A S Open-drain possible: PBODE Internal data bus PB0 (TA0IN, TXD2) Selector B S B Selector PB read TA0IN A Figure 3.5.31 Port B0 91C820A-86 2006-01-31 TMP91C820A (2) PB1 (TA1OUT, RXD2) Port B1 is I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD2, it is possible to logical invert by setting the register PB Reset Direction control (on bits basis) PBCR write Function control (on bit basis) PBFC write S Output latch PB write TA1OUT A S Internal data bus PB1 (TA1OUT, RXD2) Selector B S B Selector PB read RXD2 A Figure 3.5.32 Port B1 (3) PB3 (INT0) Reset Direction control (on bits basis) PBCR write Internal data bus Function control (on bits basis) PBFC write S Output latch PB write SB Selector PB read A Level/edge select and rising/falling select IIMC INT0 Figure 3.5.33 Port B3 91C820A-87 2006-01-31 TMP91C820A (4) PB4 (INT1), PB5 (INT2, TA3OUT), PB6 (INT3, TB0OUT0) Reset Direction control (on bits basis) PBCR write Function control (on bit basis) PBFC write Internal data bus S Output latch PB write S B PB4 (INT1) Selector PB read A INT1 Rising/falling edge detection IIMC Reset Direction control (on bits basis) PBCR write Function control (on bit basis) PBFC write Internal data bus S Output latch PB write TA3OUT TB0OUT0 PB read A S Selector B S B PB5 (INT2, TA3OUT) PB6 (INT3, TB0OUT0) Selector A INT2 to INT3 Rising/falling edge detection IIMC< I2EDGE, I3EDGE > Figure 3.5.34 PB4 to PB6 91C820A-88 2006-01-31 TMP91C820A Port B Register 7 PB (0022H) Bit symbol Read/Write After reset Function 6 PB6 5 PB5 R/W 4 PB4 3 PB3 2 1 PB1 R/W 0 PB0 Data from external port (Output latch register is set to 1.) Data from external port (Output latch register is set to 1.) - - - - (Note 3) - Port B Control Register 7 PBCR (0024H) Bit symbol Read/Write After reset Function 6 PB6C 0 5 PB5C W 0 0: Input 4 PB4C 0 1: Output 3 PB3C 0 2 1 PB1C W 0 0 PB0C 0 0: Input 1: Output Port B Function Register 7 PBFC (0025H) Bit symbol Read/Write After reset Function 6 PB6F 0 0: Port 1: INT3 TB0OUT0 5 PB5F W 0 0: Port 1: INT2 TA3OUT 4 PB4F 0 0: Port 1: INT1 3 PB3F 0 0: Port 1: INT0 2 1 PB1F W 0 0: Port 1: TA1OUT 0 PB0F 0 0:Port 1:TXD2 INT2, TA3OUT setting 0 Input port INT2 1 Output port TA3OUT INT3, TB0OUT0 setting 0 Input port INT3 1 Output port TB0OUT0 Port B ODE Register 7 PBODE (002BH) Bit symbol Read/Write After reset Function 6 5 4 3 2 1 0 ODEPB0 W 0 TXD2 0: CMOS 1: Open drain Note 1: Read-modify-write is prohibited for the registers PBCR, PBFC and PBODE. Note 2: PB0/TA0IN pin does not have a register changing PORT/FUNCTION. For example, when it is used as an input port, the input signal is inputted to 8-bit timer. Note 3: PB1/RXD1 pin does not have a register changing PORT/FUNCTION. For example, when it is used as an input port, the input signal is inputted to SIO as the serial receive data. Figure 3.5.35 Register for Port B 91C820A-89 2006-01-31 TMP91C820A 3.5.14 Port C (PC0 to PC5) Port C0 to C5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PC0 to PC5 to be an input ports. It also sets all bits of the output latch register to 1. In addition to functioning as general-purpose I/O port pins, PC0 to PC5 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing a 1 to the corresponding bit of the port C function register (PCFC). Resetting resets all bits of the registers PCCR and PCFC to 0 and sets all pins to be input ports. (1) Port C0, C3 (TXD0/TXD1) As well as functioning as I/O port pins, port C0 and C3 can also function as serial channel TXD output pins. In case of use TXD0/TXD1, it is possible to logical invert by setting the register PC Reset Direction control (on bit basis) PCCR write Internal data bus Function control (on bit basis) PCFC write S Output latch PC write TXD0, TXD1 Logical invert A S PC0 (TXD0) PC3 (TXD1) Selector B S B PC read Selector A Open-drain possible: PCODE Figure 3.5.36 Port C0 and Port C3 91C820A-90 2006-01-31 TMP91C820A (2) Port C1, C4 (RXD0, 1) Port C1 and C4 are I/O port pins and can also be used as RXD input for the serial channels. In case of use RXD0/RXD1, it is possible to logical invert by setting the register PC Reset Ditection control (on bit basis) Internal data bus PCCR write S Output latch PC write PC read RXD0, RXD1 Logical invert PC1 (RXD0) PC4 (RXD1) S B Selector A Figure 3.5.37 Port C1 and Port C4 (3) Port C2 ( CTS0 , SCLK0), C5 ( CTS1 , SCLK1) Port C2 and C4 are I/O port pins and can also be used as CTS input or SCLK input/output for the serial channels. In case of use CTS , SCLK, it is possible to logical invert by setting the register PC Reset Ditection control (on bit basis) PCCR write Internal data bus Function control (on bit basis) PCFC write S Output latch PC write Logical invert A S PC2 (SCLK0, CTS0 ) PC5 (SCLK1, CTS1 ) Selector B SCLK0, SCLK1 output SB Selector PC read CTS0 CTS1 A , , SCLK0, SCLK1 input Logical invert Figure 3.5.38 Port C2 and Port C5 91C820A-91 2006-01-31 TMP91C820A Port C Register 7 PC (0023H) Bit symbol Read/Write After reset 6 5 PC5 4 PC4 3 PC3 R/W 2 PC2 1 PC1 0 PC0 Data from external port (Output latch register is set to 1.) Port C Control Register 7 PCCR (0026H) Bit symbol Read/Write After reset Function 6 5 PC5C 0 4 PC4C 0 3 PC3C W 0 0: Input 2 PC2C 0 1: Output 1 PC1C 0 0 PC0C 0 Port C Functon Register 7 PCFC (0027H) Bit symbol Read/Write After reset Function 6 5 PC5F W 0 0: Port 1: SCLK1 output 4 3 PC3F W 0 0: Port 1: TXD1 2 PC2F W 0 0: Port 1: SCLK0 output 1 0 PC0F W 0 0: Port 1: TXD0 Port C ODE Register 7 PCODE (0028H) Bit symbol Read/Write After reset Function 6 5 4 3 ODEPC3 W 0 TXD1 0: CMOS 1: Open drain 2 1 0 ODEPC0 W 0 TXD0 0: CMOS 1: Open drain Note 1: Read-modify-write is prohibited for the registers PCCR, PCFC and PCODE. Note 2: PC1/RXD0, PC4/RXD1 pins do not have a register changing PORT/FUNCTION. For example, when it is used as an input port, the input signal is inputted to SIO as the serial receive data. Figure 3.5.39 Register for Port C 91C820A-92 2006-01-31 TMP91C820A 3.5.15 Port D (PD0 to PD7) Port D is an 8-bit output port. Resetting sets the output latch PD to 1, and PD0 to PD7 pin output 1. In addition to functioning as output port, port D also function as output pin for LCD controller (DIBSCP, D2BLP, D3BFR, DLEBCD and DOFFB), output pin for RTC alarm ( ALARM ) and output pin for melody/alarm generator (MLDALM, MLDALM ). Above setting is used the function register PDFC. Only PD6 has two output function which are ALARM and MLDALM . This selection is used PD Reset Function control Internal data bus (on bit basis) PDFC write S Output latch Selector A B PD write D1BSCP, D2BLP, D3BFR, DLEBCD, DOFFB, MLDALM PD read PD0 (D1BSCP), PD1 (D2BLP), PD2 (D3BFR), PD3 (DLEBCD), PD4 (DOFFB), PD7 (MLDALM) Output buffer Figure 3.5.40 Port D0 to D4, D7 Reset Function control (on bit basis) PDFC write Internal data bus S Output latch S A Y Selector B PD6 ( ALARM , MLDALM ) PD write PD read MLDALM ALARM A S Y Selector B Figure 3.5.41 Port D6 91C820A-93 2006-01-31 TMP91C820A Port D Register 7 PD (0029H) Bit symbol Read/Write After reset 1 PD7 R/W 6 PD6 1 5 4 PD4 1 3 PD3 1 2 PD2 R/W 1 1 PD1 1 0 PD0 1 Port D Function Register 7 PDFC (002AH) Bit symbol Read/Write After reset Function 0: Port 1: MLDALM 6 PD6F W 0 0: Port 1: ALARM at 5 4 PD4F 3 PD3F 2 PD2F W 0 1 PD1F 0 PD0F PD7F 0: Port 1: DOFFB 0: Port 1: DLEBCD 0: Port 1: D3BFR 0: Port 1: D2BLP 0: Port 1: D1BSCP Note: Read-modify-write is prohibited for the registers PDFC. Figure 3.5.42 Register for Port D 91C820A-94 2006-01-31 TMP91C820A 3.5.16 Port E (PE0 to PE7) Port E is an 8-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PECR. Resetting, the control register PECR to 0 and sets Port E to input ports. It also sets all bits of the output latch register to 1. In addition to functioning as a general-purpose I/O port, port E can also function as an data bus for LCD controller (LD0 to LD7). Above setting is used the function register PEFC. Reset Direction control (on bit basis) PECR write Function control (on bit basis) PEFC write S Output latch PE write LD7 to LD0 Internal data bus A S PE0 to PE7 (LD0 to LD7) Selector B SB Selector PE read A Figure 3.5.43 Port E Port E Register 7 PE (002CH) Bit symbol Read/Write After reset PE7 6 PE6 5 PE5 4 PE4 R/W 3 PE3 2 PE2 1 PE1 0 PE0 Data from external port (Output latch register is set to 1.) Port E Control Register 7 PECR (002DH) Bit symbol Read/Write After reset Function 0 PE7C 6 PE6C 0 5 PE5C 0 4 PE4C W 0 0: Input 3 PE3C 0 1: Output 2 PE2C 0 1 PE1C 0 0 PE0C 0 Port E Function Register 7 PEFC (002EH) Bit symbol Read/Write After reset Function 0 PE7F 6 PE6F 0 5 PE5F 0 0: Port 4 PE4F W 0 3 PE3F 0 2 PE2F 0 1 PE1F 0 0 PE0F 0 1: Data bus for LCDC (LD7 to LD0) Note: Read-modify-write is prohibited for PECR and PEFC. Figure 3.5.44 Register for Port E 91C820A-95 2006-01-31 TMP91C820A 3.5.17 Port F (PF0 to PF7) Port F is an 8-bit output port. Resetting sets the output latch PF to 1, and PF0 to PF7 pin output 1. In addition to functioning as output port, port F also function as output pin for SDRAM controller (SDCKE, SDCLK, SDLDQM, SDUDQM, SDWE ), and output pin for SSIO (SSCLK). Above setting is used the function register PFFC. Reset Function control (on bit basis) Internal data bus PFFC write S Output latch Selector A B Output buffer PF write SDRAS , SDCAS , SDWE , SDLDQM, SDUDQM, SDCKE, SDCLK PF0 ( SDRAS ) PF1 ( SDCAS ) PF2 ( SDWE ) PF3 (SDLDQM) PF4 (SDUDQM) PF5 (SDCKE) PF6 (SDCLK) PF7 PF read Figure 3.5.45 Port F Port F Register 7 PF (0030H) Bit symbol Read/Write After reset 1 PF7 6 PF6 1 5 PF5 1 4 PF4 R/W 1 3 PF3 1 2 PF2 1 1 PF1 1 0 PF0 1 Port F Function Register 7 PFFC (0032H) Bit symbol Read/Write After reset Function "0". 6 PF6F 1 1: SDCLK 5 PF5F 0 0: Port 1: SDCKE 4 PF4F W 0 0: Port 3 PF3F 0 0: Port 2 PF2F 0 1 PF1F 0 0: Port 1: SDCAS 0 PF0F 0 0: Port 1: SDRAS - 0 Always write 0: Port 0: Port 1: SDUDQM 1: SDLDQM 1: SDWE Note: Read-modify-write is prohibited for the registers PFFC. Figure 3.5.46 Register for Port F 91C820A-96 2006-01-31 TMP91C820A 3.6 Chip Select/Wait Controller On the TMP91C820A, four user-specifiable address areas ( CS0 to CS3 ) can be set. The data bus width and the number of waits can be set independently for each address area ( CS0 to CS3 and others). The pins CS0 to CS3 (which can also function as port pins P60 to P63) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the port 6 function register (P6FC) must be set. CS2A to CS2G and CSEXA (CS pin except CS0 to CS3 ) are made by MMU. These pins are CS pin that area and BANK value is fixed without concern in setting of CS/WAIT controller. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin controlling these states is the bus wait request pin ( WAIT ). 3.6.1 Specifying an Address Area The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and memory address mask registers (MAMR0 to MAMR3). At each bus cycle, a compare operation is performed to determine if the address on the specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the corresponding CS area. In this case, the CS0 to CS3 pin outputs the chip select signal and the bus cycle operates in accordance with the settings in chip select/wait control register B0CS to B3CS. (See 3.6.2 "Chip Select/Wait Control Registers".) 91C820A-97 2006-01-31 TMP91C820A (1) Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper eight bits (A23 to A16) of the start address in Memory Start Address Registers (for areas CS0 to CS3) 7 MSAR0 (00C8H) MSAR2 (00CCH) MSAR1 Bit symbol (00CAH) Read/Write MSAR3 After reset (00CEH) Function S23 1 6 S22 1 5 S21 1 4 S20 R/W 1 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.6.1 Memory Start Address Register Start address Address 000000H 64 Kbytes Value in start address register (MSAR0 to MSAR3). 000000H .................... 00H 010000H .................... 01H 020000H .................... 02H 030000H .................... 03H 040000H .................... 04H 050000H .................... 05H 060000H .................... 06H to to FF0000H .................... FFH FFFFFFH Figure 3.6.2 Relationship between Start Address and Start Address Register Value 91C820A-98 2006-01-31 TMP91C820A (2) Memory address mask registers Figure 3.6.3 shows the memory address mask registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in memory start address registers MAMR0 to MAMR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to 0 in these registers. Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to CS3 areas. Accordingly, the size that can be each area is different. Memory Address Mask Register (for CS0 area) 7 MAMR0 (00C9H) Bit symbol Read/Write After reset Function 1 V20 6 V19 1 5 V18 1 4 V17 R/W 1 3 V16 1 2 V15 1 1 V14 to V9 1 0 V8 1 Sets size of CS0 area 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes Memory Address Mask Register (CS1) 7 MAMR1 Bit symbol (00CBH) Read/Write After reset Function V21 1 6 V20 1 5 V19 1 4 V18 R/W 1 3 V17 1 2 V16 1 1 V15 to V9 1 0 V8 1 Sets size of CS1 area 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2, CS3) 7 MAMR2 (00CDH) MAMR3 Bit symbol (00CFH) Read/Write After reset Function V22 1 6 V21 1 5 V20 1 4 V19 R/W 1 3 V18 1 2 V17 1 1 V16 1 0 V15 1 Sets size of CS2 or CS3 area 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.6.3 Memory Address Mask Registers 91C820A-99 2006-01-31 TMP91C820A (3) Setting memory start addresses and address areas Figure 3.6.4 shows an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set 01H in memory start address register MSAR0 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address CS0 area size (64 Kbytes) Memory start address S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 H V20 V19 V18 V17 V16 V15 V14 to V9 V8 MSMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.6.4 Example Showing How to Set the CS0 Area After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to FFH. B0CS 91C820A-100 2006-01-31 TMP91C820A (4) Address area size specification Table 3.6.1 shows the relationship between CS area and area size. "" indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination indicated by "", set the start address mask register in the desired steps starting from 000000H. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the smaller CS area number has the higher priority. Example: To set the area size for CS0 to 128 Kbytes: a. Valid start addresses 000000H 020000H 040000H 060000H : 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. b. Invalid start addresses 000000H 010000H 030000H 050000H : 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. Table 3.6.1 Valid Area Sizes for Each CS Area Size (bytes) CS area CS0 CS1 CS2 CS3 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M Note: "" indicates areas that cannot be set by memory start address register and address mask register combinations. 3.6.2 Chip Select/Wait Control Registers Figure 3.6.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 and others) are set in their respective chip select/wait control registers, B0CS to B3CS and BEXCS. 91C820A-101 2006-01-31 TMP91C820A Chip Select/Wait Control Registers 7 B0CS (00C0H) Readmodifywrite instructions are prohibited. 6 5 B0OM1 0 4 B0OM0 0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 1 B0W1 0 0 B0W0 0 Bit symbol Read/Write After reset Function B0E W 0 0: Disable 1: Enable Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don't care 11: 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits B1CS (00C1H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function B1E W 0 0: Disable 1: Enable B1OM1 0 B1OM0 0 B1BUS W 0 Data bus width 0: 16 bits 1: 8 bits B1W2 0 B1W1 0 B1W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don't care 11: Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits B2CS (00C2H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function B2E 1 0: Disable 1: Enable B2M 0 CS2 area selection 0: 16-Mbyte area 1: CS area B2OM1 0 B2OM0 W 0 B2BUS 0 Data bus width 0: 16 bits 1: 8 bits B2W2 0 B2W1 0 B2W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don't care 11: Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits B3CS (00C3H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function B3E W 0 0: Disable 1: Enable B3OM1 0 B3OM0 0 B3BUS W 0 Data bus width 0: 16 bits 1: 8 bits B3W2 0 B3W1 0 B3W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don't care 11: Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits BEXCS (00C7H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits BEXW2 0 0 BEXW1 0 BEXW0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits Master enable bit Chip select output waveform selection Number of address area waits (See 3.6.2 (3) "Wait control".) 0 1 Disable Enable 00 For ROM/SRAM 01 10 Don't care 11 CS2 area selection 0 1 16-Mbyte area Specified address area Data bus width selection 0 1 16-bit data bus 8-bit data bus Figure 3.6.5 Chip Select/Wait Control Registers 91C820A-102 2006-01-31 TMP91C820A (1) Master enable bits Bit 7 ( (2) Data bus width selection Bit 3 ( 91C820A-103 2006-01-31 CPU Data D15 to D8 RD WR HWR SRLB SRUB SRWR RD WR HWR SRLB Control for READ Cycle R/W R/W SRUB Control for WRITE Cycle SRWR Operand Operand Memory CPU Data Start Data Bus Address Bus Address Width Width D7 to D0 b7 to b0 L XXXX XXXX b7 to b0 XXXX XXXX L L L H L H L H H H L H H L H L H b15 to b8 XXXX XXXX b7 to b0 XXXX XXXX b15 to b8 b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 XXXX H L H b7 to b0 L H L H L b7 to b0 L H H L H L H L H XXXX 2n + 0 8 bits 2n + 0 (Even number) 16 bits 2n + 0 8 bits 2n + 1 (Odd number) 8 bits 2n + 1 16 bits 2n + 1 2n + 0 8 bits (Even number) 2n + 0 2n + 1 L L L H L H L H L H L L L H L H L H L H L 16 bits 2n + 0 16 bits Table 3.6.2 Dynamic Bus Sizing xxxx: Indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for these bits goes to high impedance; also, that the write strobe signal for the bus remains inactive. XXXX XXXX XXXX XXXX L b15 to b8 b31 to b24 b7 to b0 b23 to b16 L b7 to b0 b15 to b8 b23 to b16 b31 to b24 H L H L H L L L L L XXXX XXXX XXXX XXXX b7 to b0 XXXX b23 to b16 b15 to b8 XXXX b31 to b24 b7 to b0 b15 to b8 b23 to b16 b31 to b24 L H L H L H H L L L L H H L L L L H H L L L L H 91C820A-104 2n + 1 (Odd number) 8 bits 2n + 1 2n + 2 16 bits 2n + 1 2n + 2 2n + 0 8 bits (Even number) 2n + 0 2n + 1 2n + 2 2n + 3 16 bits 2n + 0 2n + 2 32 bits 8 bits 2n + 1 (Odd number) 2n + 1 2n + 2 2n + 3 2n + 4 TMP91C820A 16 bits 2n + 1 2n + 2 2n + 4 2006-01-31 TMP91C820A (3) Wait control Bits 0 to 2 ( 000 001 010 Number of Waits 2 waits 1 wait (1 + N) waits Wait Operation Inserts a wait of 2 states, irrespective of the WAIT pin state. Inserts a wait of 1 state, irrespective of the WAIT pin state. Samples the state of the WAIT pin after inserting a wait of one state. If the WAIT pin is low, the waits continue and the bus cycle is extended until the pin goes high. Ends the bus cycle without a wait, regardless of the WAIT pin state. Invalid setting Inserts a wait of 3 states, irrespective of the WAIT pin state. Inserts a wait of 4 states, irrespective of the WAIT pin state. Inserts a wait of 8 states, irrespective of the WAIT pin state. 011 100 101 110 111 0 waits Reserved 3 waits 4 waits 8 waits A reset sets these bits to 000 (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations, which are not in one of the four users specified address areas (CS0 to CS3), are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS 91C820A-105 2006-01-31 TMP91C820A If a CS0 to S3 address is specified which is actually an internal I/O and RAM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins. Example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 = 01H .......... Start address: 010000H MAMR0 = 07H ......... Address area: 64 Kbytes B0CS = 83H ............. ROM/SRAM, 16-bit data bus, 0 waits, CS0 area settings enabled 3.6.3 Connecting External Memory Figure 3.6.6 shows an example of how to connect external memory to the TMP91C820A. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C820A CS0 CS1 CS2 OE Address bus CS Upper byte ROM CS Lower byte ROM OE CS 8-bit RAM OE WE CS 8-bit I/O OE WE A0 to A23 A0-A23 D8 to D15 D0 to D7 RD WR Figure 3.6.6 Example of External Memory Connection (ROM uses 16-bit bus; RAM and I/O use 8-bit bus.) A reset clears all bits of the port 6 control register (P6CR) and the port 6 function register (P6FC) to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to 1. 91C820A-106 2006-01-31 TMP91C820A TMP91C820A 16-bit SRAM OE LDS UDS RD SRLB SRUB SRWR CS0 R/W CE D [15:0] A0 A1 A2 A3 ... ... Not connect I/O [16:1] A0 A1 A2 ... Figure 3.6.7 How to Connect to 16-Bit SRAM for TMP91C820A 91C820A-107 2006-01-31 TMP91C820A 3.7 8-Bit Timers (TMRA) The TMP91C820A features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. * * * * 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Figure 3.7.1 and 3.7.2 show block diagrams for TMRA01 and TMRA23. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five controls SFRs (Special function registers). Each of the two modules (TMRA01 and TMRA23) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows. 3.7.1 Block Diagrams 3.7.2 Operation of Each Circuit 3.7.3 SFRs 3.7.4 Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM (Pulse width modulation) output mode (5) Settings for each mode (6) LCDC and MELODY/ALARM circuit supply mode Table 3.7.1 Registers and Pins for Each Module Module Input pin for external clock Output pin for timer flip-flop Timer run register SFR (Address) Timer register Timer mode register Timer flip-flop control register TMRA01 TA0IN (Shared with PB0) TA1OUT (Shared with PB1) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TMRA23 No TA3OUT (Shared with PB5) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) External pin 91C820A-108 2006-01-31 3.7.1 Prescaler 2 T1 Timer flip-flop TA1FF TA01RUN over flow n Prescaler clock: T0 4 T4 T16 T256 8 16 32 64 128 256 512 Block Diagrams Run/clear TA01RUN Selector T1 T16 T256 8-bit up counter (UC1) TA01MOD TA01RUN Timer flip-flop output: TA1OUT External input clock: TA0IN Figure 3.7.1 TMRA01 Block Diagram TA01MOD 91C820A-109 8-bit comparator (CP0) TA01MOD Match 8-bit comparator detect (CP1) 8-bit timer register TA1REG Internal bus TMRA1 interrupt output: INTTA1 TMP91C820A 2006-01-31 Prescaler Prescaler clock: T0 2 T1 T256 Timer flip-flop TA3FF TA23RUN n 4 T4 T16 8 16 32 64 128 256 512 Run/clear TA23RUN Selector T1 T16 T256 8-bit up counter (UC3) TA23RUN Timer flip-flop output: TA3OUT (Supply to MLD, LCDC) Figure 3.7.2 TMRA23 Block Diagram TA23MOD 91C820A-110 Match 8-bit comparator detect (CP2) TA2TR TA23MOD Match 8-bit comparator detect (CP3) 8-bit timer register TA3REG Internal bus TMRA3 interrupt output: INTTA3 TMP91C820A 2006-01-31 TMP91C820A 3.7.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The clock T0 is divided by 4 and input to this prescaler. T0 can be either fFPH or fc/16 and is selected using the prescaler clock selection register SYSCR0 Table 3.7.2 Prescaler Output Clock Resolution at fc = 36 MHz, fs = 32.768 kHz System Prescaler Clock Gear Value Clock Selection 1 (fs) 00 (fFPH) 0 (fc) 10 (fc/16 CLOCK) xxx: Don't care XXX 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) XXX 3 3 4 5 6 7 Prescaler Output Clock Resolution T1 2 /fs (244 s) 2 /fc (0.2 s) 2 /fc (0.4 s) 2 /fc (0.9 s) 2 /fc (1.8 s) 2 /fc (3.6 s) 2 /fc (3.6 s) 7 5 T4 7 7 8 9 T16 11 11 12 13 14 15 T256 2 /fs (62.5 ms) 2 /fc (56.9 s) 2 /fc (113.8 s) 2 /fc (227.6 s) 2 /fc (455.1 s) 2 /fc (910.2 s) 2 /fc (910.2 s) 15 2 /fs (977 s) 2 /fs (3.9 ms) 2 /fc (0.9 s) 2 /fc (3.6 s) 5 6 7 8 2 /fc (1.8 s) 2 /fc (7.1 s) 2 /fc (3.6 s) 2 /fc (14.2 s) 2 /fc (7.1 s) 2 /fc (28.4 s) 10 11 2 /fc (14.2 s) 2 /fc (56.9 s) 9 2 /fc (14.2 s) 2 /fc (56.9 s) 9 11 (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4 or T16. The clock setting is specified by the value set in TA01MOD 91C820A-111 2006-01-31 TMP91C820A (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN Selector B Y Shift trigger Register buffers 0 Write Internal data bus TA01RUN Timer registers 0 (TA0REG) Figure 3.7.3 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When The address of each timer register is as follows. TA0REG: 000102H TA2REG: 00010AH TA1REG: 000103H TA3REG: 00010BH All these registers are write only and cannot be read. 91C820A-112 2006-01-31 TMP91C820A (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR Match between TA0REG and up-counter 2 overflow interrupt (INTTA0) TA1OUT tPWM (PWM cycle) Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt n 91C820A-113 2006-01-31 TMP91C820A 3.7.3 SFRs TMRA01 Run Register 7 TA01RUN (0100H) Bit symbol Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 6 5 4 3 I2TA01 0 2 TA01PRUN 1 TA1RUN 0 R/W 0 TA0RUN 0 0 8-bit timer run/stop control IDLE2 0: Stop and clear 0: Stop 1: Operate 1: Run (Count up) TA0REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop and clear Run (Count up) I2TA01: Operation in IDLE2 mode TA01PRUN: Run prescaler TA1RUN: Run TMRA1 TA0RUN: Run TMRA0 Note: The values of bits 4 to 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN (0108H) Bit symbol Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable 6 5 4 3 I2TA23 0 2 TA23PRUN 1 TA3RUN 0 R/W 0 TA2RUN 0 0 8-bit timer run/stop control IDLE2 0: Stop and clear 0: Stop 1: Operate 1: Run (Count up) TA2REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop and clear Run (Count up) I2TA23: Operation in IDLE2 mode TA23PRUN: Run prescaler TA3RUN: Run TMRA3 TA2RUN: Run TMRA2 Note: The values of bits 4 to 6 of TA23RUN are undefined when read. Figure 3.7.4 Register for TMRA 91C820A-114 2006-01-31 TMP91C820A TMRA01 Mode Register 7 TA01MOD Bit symbol (0104H) Read/Write After reset Function TA01M1 0 Operation mode 6 TA01M0 0 5 PWM01 0 PWM cycle 00: Reserved 6 01: 2 10: 2 11: 2 7 8 4 PWM00 0 R/W 3 TA1CLK1 0 00: TA0TRG 01: T1 10: T16 11: T256 2 TA1CLK0 0 1 TA0CLK1 0 00: TA0IN pin 01: T1 10: T4 11: T16 0 TA0CLK0 0 Source clock for TMRA1 Source clock for TMRA0 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA0 source clock selection 00 01 10 11 TA0IN (External input) T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA1 source clock selection TA01MOD Comparator output from TMRA0 TA01MOD Overflow output from TMRA0 T1 T16 (16-bit timer mode) 11 T256 PWM cycle selection 00 01 10 Reserved 2 x source clock 6 7 8 2 x source clock 11 2 x source clock TMRA01 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0) + 8-bit timer (TMRA1) Figure 3.7.5 Register for TMRA 91C820A-115 2006-01-31 TMP91C820A TMRA23 Mode Register 7 TA23MOD Bit symbol (010CH) Read/Write After reset Function TA23M1 0 Operation mode 6 TA23M0 0 5 PWM21 0 PWM cycle 00: Reserved 6 01: 2 10: 2 11: 2 7 8 4 PWM20 0 R/W 3 TA3CLK1 0 00: TA2TRG 01: T1 10: T16 11: T256 2 TA3CLK0 0 1 TA2CLK1 0 00: Reserved 01: T1 10: T4 11: T16 0 TA2CLK0 0 TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA2 source clock selection 00 01 10 11 Do not set T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA3 source clock selection TA23MOD PWM cycle selection 00 01 10 11 Reserved 2 x source clock 6 7 8 2 x source clock 2 x source clock TMRA23 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA2) + 8-bit timer (TMRA3) Figure 3.7.6 Register for TMRA 91C820A-116 2006-01-31 TMP91C820A TMRA1 Flip-Flop Control Register 7 TA1FFCR (0105H) Bit symbol Read/Write After reset Function Readmodifywrite instructions are prohibited. 6 5 4 3 TA1FFC1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don't care R/W 2 TA1FFC0 1 1 TA1FFIE 0 TA1FF control for inversion 0: Disable 1: Enable R/W 0 TA1FFIS 0 TA1FF inversion select 0: TMRA0 1: TMRA1 Inverse signal for timer flip-flop 1 (TA1FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA0 Inversion by TMRA1 Inversion of TA1FF 0 1 Disabled Enabled Control of TA1FF 00 01 10 11 Inverts the value of TA1FF Sets TA1FF to 1 Clears TA1FF to 0 Don't care Figure 3.7.7 Register for TMRA 91C820A-117 2006-01-31 TMP91C820A TMRA3 Flip-Flop Control Register 7 TA3FFCR (010DH) Bit symbol Read/Write After reset Function Readmodifywrite instructions are prohibited. 6 5 4 3 TA3FFC1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don't care R/W 2 TA3FFC0 1 1 TA3FFIE 0 TA3FF control for inversion 0: Disable 1: Enable R/W 0 TA3FFIS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 Inverse signal for timer flip-flop 3 (TA3FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA2 Inversion by TMRA3 Inversion of TA3FF 0 1 Disabled Enabled Control of TA3FF 00 01 10 11 Inverts the value of TA3FF Sets TA3FF to 1 Clears TA3FF to 0 Don't care Figure 3.7.8 Register for TMRA 91C820A-118 2006-01-31 TMP91C820A TMRA register 7 TA0REG (0102H) bit Symbol Read/Write After reset TA1REG (0103H) bit Symbol Read/Write After reset TA2REG (010AH) bit Symbol Read/Write After reset TA3REG (010BH) bit Symbol Read/Write After reset 6 5 4 - W Undefined - W Undefined - W Undefined - W Undefined 3 2 1 0 Note: The above registers are prohibited read-modify-write instruction. Figure 3.7.9 Register for TMRA 91C820A-119 2006-01-31 TMP91C820A 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. a. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 8.0 s at fc = 36 MHz, set each register as follows: * Clock state System clock: High frequency (fc) Prescaler clock: fFPH MSB 7 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN - 0 0 X - 6 - 0 0 1 X 5 X X 1 0 X 4 X X 0 1 X 3 - 1 1 - - LSB 2 - 0 0 - 1 1 0 - 0 - 1 0 - - 0 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.2 s at fc = 36 MHz) as the input clock. Set TA1REG to 8.0 s / T1 = 40 = 28H. Enable INTTA1 and set it to level 5. Start TMRA1 counting. X: Don't care, -: No change Select the input clock using Table 3.7.2. Note: The input clocks for TMRA0 and TMRA1 are different from as follows. TMRA0: TA0IN input, T1, T4 or T16. TMRA1: Match output of TMRA0, T1, T16, T256. 91C820A-120 2006-01-31 TMP91C820A b. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.2 s square wave pulse from the TA1OUT pin at fc = 36MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. * Clock state System clock: Clock gear: High frequency (fc) 1 (fc) Prescaler clock: fFPH 7 TA01RUN TA01MOD TA1REG TA1FFCR PBCR PBFC TA01RUN - 0 0 X X X - 6 X 0 0 X - - X 5 X X 0 X - - X 4 X X 0 X - - X 3 - 0 0 1 - - - 2 - 1 0 0 X X 1 1 0 - 1 1 1 1 1 0 - - 1 1 - - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.2 s at fc = 36 MHz) as the input clock. Set the timer register to 1.2 s / T1 / 2 = 3. Clear TA1FF to 0 and set it to invert on the match detects signal from TMRA1. Set PB1 to function as the TA1OUT pin. Start TMRA1 counting. X: Don't care, -: No change T1 TA01RUN 0 1 2 3 0 1 2 3 0 1 2 3 0 TA1FF TA1OUT 0.6 s at fc = 36 MHz Figure 3.7.10 Square Wave Output Timing Chart (50% duty) 91C820A-121 2006-01-31 TMP91C820A c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up counter (When TA0REG = 5) TMRA1 up counter (When TA1REG = 2) TMRA1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.11 TMRA1 Count Up on Signal from TMRA0 91C820A-122 2006-01-31 TMP91C820A (2) 16-bit timer mode Pairing the two 8-bit timers TMRA0 and TMRA1 configures a 16-bit interval timer. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD Setting example: To generate an INTTA1 interrupt every 0.22 s at fc = 36 MHz, set the timer registers TA0REG and TA1REG as follows: * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH If T16 ((27/fc)s at 36 MHz) is used as the input clock for counting, set the following value in the registers: 0.22 s /(27/fc)s 62500 = F424H (e.g. set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1 interrupt can be generated every 0.23 [s]. The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparator TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA0 comparator match detect signal INTTA0 INTTA1 TA1OUT 0080H 0180H 0280H 0380H 0480H 0080H Inversion Figure 3.7.12 Timer Output by 16-Bit Timer Mode 91C820A-123 2006-01-31 TMP91C820A (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active-low or active-high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin. tH When tL tH Example when Figure 3.7.13 8-Bit PPG Output Waveforms 91C820A-124 2006-01-31 TMP91C820A In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN TA1OUT TA0IN T1 T4 T16 Selector TA01RUN |